Patents by Inventor Vibhor Jain

Vibhor Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10535551
    Abstract: Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p-and n-terminals formed in an i-region above a substrate.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: January 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Natalie B. Feilchenfeld, Vibhor Jain, Qizhi Liu
  • Patent number: 10530334
    Abstract: Methods of forming a shear-mode acoustic wave filter on V-shaped grooves of a [100] crystal orientation Si layer over a substrate and the resulting devices are provided. Embodiments include forming a set of V-shaped grooves in a [100] crystal orientation Si layer over a substrate; and forming a shear-mode acoustic wave filter over the V-shaped grooves, the shear-mode acoustic wave filter including a first metal layer, a thin-film piezoelectric layer, and a second metal layer, wherein the second metal layer is an IDT pattern or a sheet.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: January 7, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Humberto Campanella-Pineda, You Qian, Vibhor Jain, Anthony Stamper, Rakesh Kumar
  • Patent number: 10511143
    Abstract: Structures for integrated lasers, systems including integrated lasers, and associated fabrication methods. A ring waveguide and a seed region are arranged interior of the ring waveguide. A laser strip extends across a portion of the ring waveguide. The laser strip has an end contacting the seed region and another opposing end. The laser strip includes a laser medium and a p-n junction capable of generating electromagnetic radiation. The p-n junction of the laser strip is aligned with a portion of the ring waveguide.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John J. Ellis-Monaghan, Sebastian Ventrone, Vibhor Jain, Yves Ngu
  • Patent number: 10509244
    Abstract: Structures for an optical switch, structures for an optical router, and methods of fabricating a structure for an optical switch. A phase change layer is arranged proximate to a waveguide core, and a heater is formed proximate to the phase change layer. The phase change layer is composed of a phase change material having a first state with a first refractive index at a first temperature and a second state with a second refractive index at a second temperature. The heater is configured to selectively transfer heat to the phase change layer for transitioning between the first state and the second state.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven M. Shank, Anthony K. Stamper, John J. Ellis-Monaghan, Vibhor Jain, John J. Pekarik
  • Publication number: 20190348365
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dual thickness fuse structures and methods of manufacture. The structure includes a continuous wiring structure on a single wiring level and composed of conductive material having a fuse portion and a thicker wiring structure.
    Type: Application
    Filed: May 9, 2018
    Publication date: November 14, 2019
    Inventors: JOHN J. PEKARIK, ANTHONY K. STAMPER, VIBHOR JAIN
  • Publication number: 20190346407
    Abstract: Methods of forming a shear-mode chemical/physical sensor for liquid environment sensing on V-shaped grooves of a [100] crystal orientation Si layer and the resulting devices are provided. Embodiments include forming a set of V-shaped grooves in a [100] Si layer over a substrate; forming an acoustic resonator over and along the V-shaped grooves, the acoustic resonator including a first metal layer, a thin-film piezoelectric layer, and a second metal layer in an IDT pattern or a sheet; and forming at least one functional layer along a slope of the acoustic resonator.
    Type: Application
    Filed: May 10, 2018
    Publication date: November 14, 2019
    Inventors: Humberto CAMPANELLA-PINEDA, You QIAN, Vibhor JAIN, Anthony STAMPER, Rakesh KUMAR
  • Publication number: 20190348966
    Abstract: Methods of forming a shear-mode acoustic wave filter on V-shaped grooves of a [100] crystal orientation Si layer over a substrate and the resulting devices are provided. Embodiments include forming a set of V-shaped grooves in a [100] crystal orientation Si layer over a substrate; and forming a shear-mode acoustic wave filter over the V-shaped grooves, the shear-mode acoustic wave filter including a first metal layer, a thin-film piezoelectric layer, and a second metal layer, wherein the second metal layer is an IDT pattern or a sheet.
    Type: Application
    Filed: May 10, 2018
    Publication date: November 14, 2019
    Inventors: Humberto CAMPANELLA-PINEDA, You QIAN, Vibhor JAIN, Anthony STAMPER, Rakesh KUMAR
  • Publication number: 20190340245
    Abstract: In accordance with an embodiment, described herein is a system and method for semantic analysis and use of song lyrics in a media content environment. Semantic analysis is used to identify persons, events, themes, stories, or other meaningful information within a plurality of songs. Example use cases include the selection and delivery of media content in response to input searches for songs of a particular nature; the recommendation or suggestion of media content in social messaging or other environments; or the delivery of an advertisement content based on a matching of song lyrics with advertisement topic words.
    Type: Application
    Filed: July 22, 2019
    Publication date: November 7, 2019
    Inventors: RANQI ZHU, MINWEI GU, VIBHOR JAIN
  • Patent number: 10468454
    Abstract: Methods of forming a thin-film piezoelectric acoustic filter, a GaN-channel/buffer Bragg reflector, and a monolithically integrated GaN HEMT PA and CMOS over a [111] crystal orientation Si handle of a SOI wafer and resulting devices are provided. Embodiments include providing a SOI wafer including a [111] crystal orientation Si handle, a BOX layer, and a top Si layer; forming a CMOS device over the top Si layer; and forming a Bragg reflector over the [111] crystal orientation Si handle wafer, the Bragg reflector including a GaN stack with alternating layers of high/low acoustic impedance.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Humberto Campanella-Pineda, Anthony Stamper, Vibhor Jain
  • Patent number: 10469041
    Abstract: A method of forming a CMOS device and a GaN PA structure on a 100 Si substrate having a surface orientated in 111 direction and the resulting device are provided. Embodiments include forming a device with a protective layer over a portion of a Si substrate; forming a V-shaped groove in the Si substrate; forming a buffer layer, a GaN layer, an AlGaN layer and a passivation layer sequentially over the Si substrate; forming trenches through the passivation and the AlGaN layers; forming second trenches through the passivation layer; forming electrode structures over portions of the passivation layer and filling the first and second trenches; removing portions of the passivation layer, the AlGaN layer and the GaN layer outside of the V-shaped groove down to the buffer layer; forming a dielectric layer over the Si substrate; and forming vias through the dielectric layer down to electrode structures and the device.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anthony Kendall Stamper, Vibhor Jain, Humberto Campanella Pineda, John Joseph Pekarik
  • Publication number: 20190333965
    Abstract: Methods of forming a thin-film piezoelectric acoustic filter, a GaN-channel/buffer Bragg reflector, and a monolithically integrated GaN HEMT PA and CMOS over a [111] crystal orientation Si handle of a SOI wafer and resulting devices are provided. Embodiments include providing a SOI wafer including a [111] crystal orientation Si handle, a BOX layer, and a top Si layer; forming a CMOS device over the top Si layer; and forming a Bragg reflector over the [111] crystal orientation Si handle wafer, the Bragg reflector including a GaN stack with alternating layers of high/low acoustic impedance.
    Type: Application
    Filed: April 25, 2018
    Publication date: October 31, 2019
    Inventors: Humberto CAMPANELLA-PINEDA, Anthony STAMPER, Vibhor JAIN
  • Publication number: 20190326411
    Abstract: Fabrication methods and device structures for a heterojunction bipolar transistor. A trench isolation region is formed that surrounds an active region of semiconductor material, a collector is formed in the active region, and a base layer is deposited that includes a first section over the trench isolation region, a second section over the active region, and a third section over the active region that connects the first section and the second section. An emitter is arranged over the second section of the base layer, and an extrinsic base layer is arranged over the first section of the base layer and the third section of the base layer. The extrinsic base layer includes a first section containing polycrystalline semiconductor material and a second section containing single-crystal semiconductor material. The first and second sections of the extrinsic base layer intersect along an interface that extends over the trench isolation region.
    Type: Application
    Filed: April 24, 2018
    Publication date: October 24, 2019
    Inventors: Vibhor Jain, Pernell Dongmo, Cameron Luce, James W. Adkisson, Qizhi Liu
  • Patent number: 10446644
    Abstract: Methods for forming a device structure and device structures using a silicon-on-insulator substrate that includes a high-resistance handle wafer. A doped region is formed in the high-resistance handle wafer. A first trench is formed that extends through a device layer and a buried insulator layer of the silicon-on-insulator substrate to the high-resistance handle wafer. The doped region includes lateral extension of the doped region extending laterally of the first trench. A semiconductor layer is epitaxially grown within the first trench, and a device structure is formed using at least a portion of the semiconductor layer. A second trench is formed that extends through the device layer and the buried insulator layer to the lateral extension of the doped region, and a conductive plug is formed in the second trench. The doped region and the plug comprise a body contact.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Renata Camillo-Castillo, Hanyi Ding, Natalie B. Feilchenfeld, Vibhor Jain, Anthony K. Stamper
  • Patent number: 10439053
    Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Vibhor Jain, Alvin J. Joseph, Qizhi Liu
  • Publication number: 20190273132
    Abstract: Structures that include an airgap and methods for forming a structure that includes an airgap. A layer stack is epitaxially grown on a substrate and includes a first semiconductor layer and a second semiconductor layer on a substrate. A plurality of openings are formed that extend through a device region of the first semiconductor layer to the second semiconductor layer. The second semiconductor layer is etched through the openings and selective to the substrate and the first semiconductor layer so as to form an airgap that is arranged in a vertical direction between the substrate and the device region. A device structure is formed in the device region of the first semiconductor layer.
    Type: Application
    Filed: March 5, 2018
    Publication date: September 5, 2019
    Inventors: Michael Zierak, Anthony K. Stamper, John J. Pekarik, Vibhor Jain
  • Publication number: 20190273028
    Abstract: Structures and methods associated with a silicon-on-insulator substrate are needed. A silicon-on-insulator substrate is provided that includes a device layer of single-crystal semiconductor material, a buried oxide layer, a handle wafer of single-crystal semiconductor material, and a non-single-crystal semiconductor layer between the handle wafer and the buried oxide layer. A trench is formed that extends through the device layer, the buried oxide layer, and the non-single-crystal semiconductor layer to the handle wafer. A semiconductor layer is epitaxially grown from the handle wafer to at least partially fill the trench, and a device structure is formed using at least a portion of the semiconductor layer.
    Type: Application
    Filed: March 2, 2018
    Publication date: September 5, 2019
    Inventors: Vibhor Jain, Anthony K. Stamper
  • Publication number: 20190267304
    Abstract: Chip packages and methods of forming a chip package. The chip package includes a power amplifier and a thermal pathway structure configured to influence transport of heat energy. The power amplifier includes a first emitter finger and a second emitter finger having at least one parameter that is selected based upon proximity to the thermal pathway structure.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 29, 2019
    Inventors: Hanyi Ding, Vibhor Jain, Alvin J. Joseph, Anthony K. Stamper
  • Patent number: 10388728
    Abstract: Structures that include an airgap and methods for forming a structure that includes an airgap. A layer stack is epitaxially grown on a substrate and includes a first semiconductor layer and a second semiconductor layer on a substrate. A plurality of openings are formed that extend through a device region of the first semiconductor layer to the second semiconductor layer. The second semiconductor layer is etched through the openings and selective to the substrate and the first semiconductor layer so as to form an airgap that is arranged in a vertical direction between the substrate and the device region. A device structure is formed in the device region of the first semiconductor layer.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Michael Zierak, Anthony K. Stamper, John J. Pekarik, Vibhor Jain
  • Publication number: 20190252530
    Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.
    Type: Application
    Filed: April 25, 2019
    Publication date: August 15, 2019
    Inventors: Vibhor Jain, Alvin J. Joseph, Qizhi Liu
  • Publication number: 20190237568
    Abstract: Fabrication methods and device structures for a silicon controlled rectifier. A cathode is arranged over a top surface of a substrate and a well is arranged beneath the top surface of the substrate. The cathode is composed of a semiconductor material having a first conductivity type, and the well also has the first conductivity type. A semiconductor layer, which has a second conductivity type opposite to the first conductivity type, includes a section over the top surface of the substrate. The section of the semiconductor layer is arranged to form an anode that adjoins the well along a junction.
    Type: Application
    Filed: January 29, 2018
    Publication date: August 1, 2019
    Inventors: Rahul Mishra, Vibhor Jain, Ajay Raman, Robert J. Gauthier