Patents by Inventor Vibhor Jain

Vibhor Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12211929
    Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an intrinsic base including a first semiconductor layer, a collector including a second semiconductor layer, and an emitter including a third semiconductor layer. The first semiconductor layer, which comprises silicon-germanium, includes a first portion and a second portion adjacent to the first portion. The second semiconductor layer includes a portion on the first portion of the first semiconductor layer, and the third semiconductor layer includes a portion on the second portion of the first semiconductor layer. The structure further comprises a dielectric spacer laterally between the portion of the second semiconductor layer and the portion of the third semiconductor layer.
    Type: Grant
    Filed: May 14, 2024
    Date of Patent: January 28, 2025
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Alexander Derrickson, Anupam Dutta, John Pekarik, Vibhor Jain, V V S S Satyasuresh Choppalli, Rui Tze Toh, Oscar Restrepo
  • Patent number: 12204144
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photonic chip security structure and methods of manufacture. The structure includes an optical component over a substrate material, and at least one vertical wall including a reflecting material within a dielectric stack of material and surrounding the optical component.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: January 21, 2025
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Nicholas A. Polomoff, Yusheng Bian, Vibhor Jain
  • Publication number: 20250015128
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.
    Type: Application
    Filed: September 24, 2024
    Publication date: January 9, 2025
    Inventors: Vibhor JAIN, Anthony K. STAMPER, John J. ELLIS-MONAGHAN, Steven M. SHANK, Rajendran KRISHNASAMY
  • Publication number: 20250006824
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted “T” shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.
    Type: Application
    Filed: September 16, 2024
    Publication date: January 2, 2025
    Inventors: Xinshu Cai, Shyue Seng Tan, Vibhor Jain, John J. Pekarik, Kien Seen Daniel Chong, Yung Fu Chong, Judson R. Holt, Qizhi Liu, Kenneth J. Stein
  • Publication number: 20240427095
    Abstract: Embodiments of the disclosure provide a multi-substrate coupling for photonic integrated circuits (PICs). Structures of the disclosure may include a first substrate having a first surface. The first surface includes a groove therein. A second substrate has a second surface coupled to the first surface. The second substrate includes a cavity substantially aligned with the groove of the first surface, and a photonic integrated circuit (PIC) structure horizontally distal to the cavity.
    Type: Application
    Filed: June 21, 2023
    Publication date: December 26, 2024
    Inventors: Ravi Prakash Srivastava, Yusheng Bian, Vibhor Jain
  • Patent number: 12176427
    Abstract: Embodiments of the disclosure provide a bipolar transistor and gate structure on a semiconductor fin and methods to form the same. A structure according to the disclosure includes a semiconductor fin including an intrinsic base region and an extrinsic base region adjacent the intrinsic base region along a length of the semiconductor fin. Sidewalls of the intrinsic base region of the semiconductor fin are adjacent an emitter and a collector along a width of the semiconductor fin. A gate structure is on the semiconductor fin and between the intrinsic base region and the extrinsic base region.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: December 24, 2024
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Shesh Mani Pandey, Vibhor Jain
  • Patent number: 12170313
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: December 17, 2024
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Vibhor Jain, Anthony K. Stamper, John J. Ellis-Monaghan, Steven M. Shank, Rajendran Krishnasamy
  • Patent number: 12159926
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.
    Type: Grant
    Filed: September 27, 2023
    Date of Patent: December 3, 2024
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Haiting Wang, Alexander Derrickson, Jagar Singh, Vibhor Jain, Andreas Knorr, Alexander Martin, Judson R. Holt, Zhenyu Hu
  • Patent number: 12159910
    Abstract: Structures with an isolation region and fabrication methods for a structure having an isolation region. The structure includes a semiconductor substrate, a first isolation region surrounding a portion of the semiconductor substrate, a device in the portion of the semiconductor substrate, and a second isolation region surrounding the first isolation region and the portion of the semiconductor substrate.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: December 3, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Uppili Raghunathan, Vibhor Jain, Sebastian Ventrone, Johnatan Kantarovsky, Yves Ngu
  • Publication number: 20240395869
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region; an emitter region above the intrinsic base region; a collector region under the intrinsic base region; and an extrinsic base region comprising metal material, and which surrounds the intrinsic base region and the emitter region.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Xinshu CAI, Shyue Seng TAN, Vibhor JAIN, John J. PEKARIK, Robert J. GAUTHIER, JR.
  • Patent number: 12142673
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted “T” shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.
    Type: Grant
    Filed: September 19, 2023
    Date of Patent: November 12, 2024
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xinshu Cai, Shyue Seng Tan, Vibhor Jain, John J. Pekarik, Kien Seen Daniel Chong, Yung Fu Chong, Judson R. Holt, Qizhi Liu, Kenneth J. Stein
  • Patent number: 12107124
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region; an emitter region above the intrinsic base region; a collector region under the intrinsic base region; and an extrinsic base region comprising metal material, and which surrounds the intrinsic base region and the emitter region.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: October 1, 2024
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xinshu Cai, Shyue Seng Tan, Vibhor Jain, John J. Pekarik, Robert J. Gauthier, Jr.
  • Publication number: 20240250158
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region; an emitter region on a first side of the extrinsic base region; a collector region on a second side of the extrinsic base region; and a gate structure comprising a gate oxide and a gate control in a same channel region as the extrinsic base region.
    Type: Application
    Filed: February 12, 2024
    Publication date: July 25, 2024
    Inventors: Judson R. Holt, Vibhor Jain, Alexander M. Derrickson
  • Publication number: 20240250157
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heater terminal contacts, methods of operation and methods of manufacture. The structure includes: a heterojunction bipolar transistor having a collector, sub-collector region, emitter and base region; and heater terminal contacts electrically coupled to the sub-collector region.
    Type: Application
    Filed: January 20, 2023
    Publication date: July 25, 2024
    Inventors: Uppili S. RAGHUNATHAN, Vibhor JAIN, Yves T. NGU, Johnatan A. KANTAROVSKY, Sebastian T. VENTRONE
  • Publication number: 20240249992
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heater elements, methods of operation and methods of manufacture. The structure includes: an active device; a heater element under the active device and within a semiconductor substrate; and a contact to the heater element and the active device.
    Type: Application
    Filed: January 20, 2023
    Publication date: July 25, 2024
    Inventors: Uppili S. RAGHUNATHAN, Vibhor JAIN, Yves T. NGU, Johnatan A. KANTAROVSKY, Sebastian T. VENTRONE
  • Patent number: 12046633
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgap structures in a doped region under one or more transistors and methods of manufacture. The structure includes: a semiconductor material comprising a doped region; one or more sealed airgap structures breaking up the doped region of the semiconductor material; and a field effect transistor over the one or more sealed airgap structures and the semiconductor material.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: July 23, 2024
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Mark D. Levy, Siva P. Adusumilli, Johnatan A. Kantarovsky, Vibhor Jain
  • Publication number: 20240234498
    Abstract: Structures for a junction field-effect transistor and methods of forming a structure for a junction field-effect transistor. The structure comprises a first gate on a top surface of a semiconductor substrate, a second gate beneath the top surface of the semiconductor substrate, and a channel region in the semiconductor substrate. The first gate is positioned between a source and a drain, and the channel region positioned between the first gate and the second gate.
    Type: Application
    Filed: October 20, 2022
    Publication date: July 11, 2024
    Inventors: Xinshu Cai, Shyue Seng Tan, Vibhor Jain, John J. Pekarik
  • Publication number: 20240231173
    Abstract: Structures including an optical phase shifter and methods of forming a structure including an optical phase shifter. The structure comprises an optical phase shifter including a waveguide core having a first branch and a second branch laterally spaced from the first branch. The structure further comprises a thermoelectric device including a first plurality of pillars and a second plurality of pillars that alternate with the first plurality of pillars in a series circuit. The first plurality of pillars and the second plurality of pillars disposed adjacent to the first branch of the waveguide core, the first plurality of pillars comprises an n-type semiconductor material, and the second plurality of pillars comprises a p-type semiconductor material.
    Type: Application
    Filed: January 9, 2023
    Publication date: July 11, 2024
    Inventors: Vibhor Jain, Yusheng Bian, Shesh Mani Pandey, Abdelsalam Aboketaf, Ravi Prakash Srivastava
  • Patent number: 12027553
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodetectors with buried airgap mirror reflectors. The structure includes a photodetector and at least one airgap in a substrate under the photodetector.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: July 2, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Siva P. Adusumilli, Vibhor Jain, Alvin J. Joseph, Steven M. Shank
  • Publication number: 20240192442
    Abstract: Structures for an edge coupler and methods of forming a structure for an edge coupler. The structure comprises a substrate, a dielectric layer over the substrate, and a waveguide core over the substrate. The structure further comprises an airgap that extends at least partially through the dielectric layer and that surrounds a plurality of sides of a portion of the waveguide core.
    Type: Application
    Filed: December 12, 2022
    Publication date: June 13, 2024
    Inventors: Ravi Prakash Srivastava, Yusheng Bian, Shesh Mani Pandey, Vibhor Jain