Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a heterojunction bipolar transistor comprising a collector region, a base region and an emitter region; and at least one non-single-crystal semiconductor region in the collector region of the heterojunction bipolar transistor.

Abstract: Structures for a junction field-effect transistor and methods of forming a structure for a junction field-effect transistor. The structure comprises a first gate on a top surface of a semiconductor substrate, a second gate beneath the top surface of the semiconductor substrate, and a channel region in the semiconductor substrate. The first gate is positioned between a source and a drain, and the channel region positioned between the first gate and the second gate.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region; an emitter region on a first side of the extrinsic base region; a collector region on a second side of the extrinsic base region; and a gate structure comprising a gate oxide and a gate control in a same channel region as the extrinsic base region.

Abstract: Techniques described herein relate to facilitating end-to-end multilingual communications with automated assistants. In various implementations, speech recognition output may be generated based on voice input in a first language. A first language intent may be identified based on the speech recognition output and fulfilled in order to generate a first natural language output candidate in the first language. At least part of the speech recognition output may be translated to a second language to generate an at least partial translation, which may then be used to identify a second language intent that is fulfilled to generate a second natural language output candidate in the second language. Scores may be determined for the first and second natural language output candidates, and based on the scores, a natural language output may be selected for presentation.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with thermal conductor and methods of manufacture. The structure includes: a base formed within a semiconductor substrate; a thermal conductive material under the base and extending to an underlying semiconductor material; an emitter on a first side of the base; and a collector on a second side of the base.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a collector contact and methods of manufacture. The structure includes: a lateral bipolar transistor which includes an emitter, a base and a collector; an emitter contact to the emitter; a base contact to the base; and a collector contact to the collector and extending to an underlying substrate underneath the collector.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with self-aligned asymmetric spacer and methods of manufacture. The structure includes: a base formed on a semiconductor substrate; an asymmetrical spacer surrounding the base; an emitter on a first side of the base and separated from the base by the asymmetrical spacer; and a collector on a second side of the base and separated from the base by the asymmetrical spacer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.

Abstract: Embodiments of the disclosure provide a bipolar transistor and gate structure on a semiconductor fin and methods to form the same. A structure according to the disclosure includes a semiconductor fin including an intrinsic base region and an extrinsic base region adjacent the intrinsic base region along a length of the semiconductor fin. Sidewalls of the intrinsic base region of the semiconductor fin are adjacent an emitter and a collector along a width of the semiconductor fin. A gate structure is on the semiconductor fin and between the intrinsic base region and the extrinsic base region.

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

Abstract: Structures for a varactor diode and methods of forming same. The structure comprises a first semiconductor layer including a section on a substrate, a second semiconductor layer on the section of the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, and a doped region in the section of the first semiconductor layer. The section of the first semiconductor layer and the doped region have a first conductivity type, and the second semiconductor layer comprises silicon-germanium having a second conductivity type opposite to the first conductivity type, and the third semiconductor layer has the second conductivity type. The doped region contains a higher concentration of a dopant of the first conductivity type than the section of the first semiconductor layer. The second semiconductor layer abuts the first section of the first semiconductor layer along an interface, and the doped region is positioned adjacent to the interface.

Abstract: Techniques described herein relate to facilitating end-to-end multilingual communications with automated assistants. In various implementations, speech recognition output may be generated based on voice input in a first language. A first language intent may be identified based on the speech recognition output and fulfilled in order to generate a first natural language output candidate in the first language. At least part of the speech recognition output may be translated to a second language to generate an at least partial translation, which may then be used to identify a second language intent that is fulfilled to generate a second natural language output candidate in the second language. Scores may be determined for the first and second natural language output candidates, and based on the scores, a natural language output may be selected for presentation.

Abstract: The disclosure provides an integrated circuit (IC) structure with fluorescent materials, and related methods. An IC structure according to the disclosure may include a layer of fluorescent material on an IC component. The layer of fluorescent material defines a portion of an identification marker for the IC structure.

Abstract: A structure includes a dielectric waveguide, and at least one grating coupler adjacent the dielectric waveguide. Each grating coupler includes a set of parallel optofluidic grating channels oriented orthogonally to the dielectric waveguide. The structure may also include a radiation source operatively coupled to the dielectric waveguide, and an optical receiver such as a photosensor adjacent the grating coupler(s). The structure may be used as part of an optofluidic sensor system for, for example, biochemical applications.

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a subcollector under a buried insulator layer; a collector above the subcollector; a base within the buried insulator layer; an emitter above the base; and contacts to the subcollector, the base and the emitter.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

Abstract: Techniques described herein relate to facilitating end-to-end multilingual communications with automated assistants. In various implementations, speech recognition output may be generated based on voice input in a first language. A first language intent may be identified based on the speech recognition output and fulfilled in order to generate a first natural language output candidate in the first language. At least part of the speech recognition output may be translated to a second language to generate an at least partial translation, which may then be used to identify a second language intent that is fulfilled to generate a second natural language output candidate in the second language. Scores may be determined for the first and second natural language output candidates, and based on the scores, a natural language output may be selected for presentation.