Abstract: A composite thyristor comprising a plurality of parallel connected identical thyristor cells, each of the cells including a turn-on field effect transistor (FET) and a turn-off FET. The gate electrodes of all the FETs form a grid-like pattern on a surface of the semiconductor substrate of the device. The pattern includes strips which intersect at corners. Turn-off FETs are formed along the boundary of the grid and beneath it, and turn-on FETs are disposed beneath the corners.

Abstract: A semiconductor device package including a cup-like base having an encircling side wall having at its upper end, a laterally, outwardly extending metal flange. A lid for the package comprises a plate-like member having, at the lower, peripheral edge thereof, an outwardly laterally extending metal flange which overlaps and is bonded to the base flange in a solderless bond. In one embodiment of the invention, the lid has apertures therethrough which are sealed by metal foils bonded to the lower surface of the lid. The metal foils overlie and are bonded to electrodes on the upper surface of the chip within the package. In another embodiment of the invention, in which the lid also has apertures therethrough, a hollow tubing extends into each aperture in hermetic fit with the aperture wall. The chip within the package includes terminal leads extending into the tubings and hermetically bonded to the tubing inner walls.

Abstract: A hermetic semiconductor package having a ceramic lid with the device leads extending vertically through the lid is disclosed. The leads are mechanically retained within the apertures in the lid and direct bonded to the lid to provide a hermetic seal and a substantial lead density.

Abstract: A hermetic semiconductor package includes a ceramic lid with the device leads extending vertically through the lid. The leads are mechanically retained within the apertures in the lid and direct bonded to the lid to provide a hermetic seal and a substantial lead density.

Abstract: Batch assembly methods for high density packaging of power semiconductor chips in hermetic thin packagings includes providing silicon chip arrays with thermocompressively bonded foil contacts, preparing ceramic lid arrays which contain upper surface and lower margin direct-bonded copper coverings and through-the-lid high current spherical conductors, coining Cu/Mo/Cu or copper cup arrays, die mounting within each respective cup a respective semiconductor chip, superpositionally registering a lid array with a strip form of cup array, and solder reflowing to hermetically seal all hermetic thin packagings within a registered set of cup and lid arrays.

Abstract: A hermetically sealed package for a semiconductor device includes a lid through which the leads of the device extend vertically away from the chip through an aperture in the lid which is hermetically sealed by the external terminal or electrode. The package is compact, lightweight and free of magnetic materials.

Abstract: A four-region semiconductor device (that is, a p-n-p-n or n-p-n-p device) including at least one further region utilizes integral FET structure for diverting carriers away from an interior region of the device and shunting them to a main current-carrying electrode of the device, whereby the device is provided with a turn-off capability. The device requires only a small amount of energy for its turn-off control gate, and utilizes a high percentage of its semiconductor body for carrying current through the device. High speed turn-off is achieved in a particular embodiment of the device.

Abstract: A hermetic, high current package for a semiconductor device includes wide flat leads which are bonded to the contact pads of the device and formed to extend through apertures in an insulating lid. The lid is sealed to a base and the apertures around the leads are sealed with solder to provide the hermetic package. This package limits lateral current flow in the contact pads of the semiconductor device to relatively low levels which ensure the integrity of the contact pads.

Abstract: A hermetically sealed package for a semiconductor device includes a lid through which the leads of the device extend vertically away from the chip through an aperture in the lid which is hermetically sealed by the external terminal or electrode. The package is compact, lightweight and free of magnetic materials.

Abstract: A self aligned method of fabricating a vertical channel insulated gate semiconductor device comprises providing a first layer of one type conductivity atop a partially processed wafer. A first protective layer is disposed over the first layer and a window is opened therethrough. A first region can be established through the first window and in the first layer. A trench is established through the first window, and extending entirely through the first region and first layer, into the partially processed wafer. An insulated gate is established in the trench to control the drift region electric field under reverse bias operation.

Abstract: An improved symmetrical blocking high voltage semiconductor device structure incorporating a sinker region and a buried region adjacent the periphery of the chip improves device operating characteristics and simplifies device fabrication processes. A heavily doped polycrystalline refill of a trench provides a deep junction sidewall region which brings the lower high voltage blocking junction to the upper surface.

Abstract: A hermetic, high current package for a semiconductor device includes wide flat leads which are bonded to the contact pads of the device and formed to extend through apertures in an insulating lid. The lid is sealed to a base and the apertures around the leads are sealed with solder to provide the hermetic package. This package limits lateral current flow in the contact pads of the semiconductor device to relatively low levels which ensure the integrity of the contact pads.

Abstract: A symmetrical blocking high breakdown voltage semiconductor device in which the lower junction termination is brought to the upper surface is fabricated by diffusing first and second regions of a first conductivity type into an upper surface of an epitaxial layer of a second conductivity type disposed on a substrate, and forming a groove having sloped sidewalls in the upper surface such that the groove extends through the second diffused region, the epitaxial layer and into the substrate. A thin layer of impurities of the first conductivity type is implanted into the sidewalls, and the impurities are electrically activated to form a low resistivity path that connects the substrate to the second diffused region. Subsequently, the semiconductor device may be separated from the wafer by cutting the wafer at the groove. The manufacturing process enables substantially complete fabrication of a plurality of devices while still in wafer form, thereby avoiding the inconvenience of processing individual dice.

Abstract: An MOS device, for self-protection from overvoltages and for protection of another circuit or component in some applications, has a semiconductor substrate which includes a drain region with a plurality of base regions disposed therein. Source regions are diffused into at least one of the base regions; at least one base region does not require any source regions and defines a sourceless base region. A diode junction, formed between the sourceless base region and the abutting drain region, undergoes junction breakdown at an avalanche voltage level chosen to cause voltage breakdown to occur between a second electrode and a gate electrode at a lower voltage level than a breakdown voltage level present between the second electrode and the first electrode when the chosen avalanche level is exceeded by a voltage applied to the device or the protected component.

Abstract: An improved conductivity vertical channel semiconductor device includes an insulated gate electrode disposed adjacent a substantial portion of the voltage supporting region. In response to an appropriate bias, the control electrode couples to the electric field originating on charges within the voltage supporting region to reorient the electric field associated with those charges toward the gate electrode and transverse to the direction of current flow through the device. Improved control of the electric field within the voltage supporting region allows the doping concentration, and hence the conductivity of the channel, to be improved without a concomitant decrease in breakdown voltage. Accordingly, the channel width and cell repeat distance of the improved device can be reduced, allowing for an improved current density to be established throughout an overall device cell structure. The charge control region of the voltage supporting layer exhibits an aspect ratio of 0.5.

Abstract: A semiconductor device having at least one P-N junction and a multiple-zone junction termination extension (JTE) region which uniformly merges with the reverse blocking junction is disclosed. The blocking junction is graded into multiple zones of lower concentration dopant adjacent termination to facilitate merging of the JTE to the blocking junction and placing of the JTE at or near the high field point of the blocking junction. Preferably, the JTE region substantially overlaps the graded blocking junction region. A novel device fabrication method is also provided which eliminates the prior art step of separately diffusing the JTE region.

Abstract: A multistage amplifying thyristor incorporates integral current control resistor regions between adjacent thyristor stages for limiting turn-on current in all but the main thyristor stage. The thyristor is essentially immune from di/dt turn-on failure without the need for external circuitry to limit di/dt in the thyristor. Modulation of the current control resistor region during turn-on is prevented by adequately spacing or shielding the region from the emitter of each thyristor stage as well as by adequate spacing or shielding of the resistor region from a portion of the lowermost emitter region containing a turn-on plasma of the preceding thyristor stage.

Abstract: A semiconductor hermetic package for semiconductor device comprises base, sidewall and cover members. Signals can be coupled between the enclosed devices and external devices by coupling means including conductive regions disposed in and through the package. Light pipes or conductive tracks and paths extending through the package can be used to couple the signals. A portion of the package can function as a grading resistance.

Abstract: A symmetrical blocking high breakdown voltage semiconductor device in which the lower junction termination is brought to the upper surface is fabricated by diffusing first and second regions of a first conductivity type into an upper surface of an epitaxial layer of a second conductivity type disposed on a substrate, and forming a groove having sloped sidewalls in the upper surface such that the groove extends through the second diffused region, the epitaxial layer and into the substrate. A thin layer of impurities of the first conductivity type is implanted into the sidewalls, and the impurities are electrically activated to form a low resistivity path that connects the substrate to the second diffused region. Subsequently, the semiconductor device may be separated from the wafer by cutting the wafer at the groove. The manufacturing process enables substantially complete fabrication of a plurality of devices while still in wafer form, thereby avoiding the inconvenience of processing individual dice.

Abstract: A large area solid state multi-layer semiconductive switching device having multiple parallel contacts accommodates large magnitudes of currents and provides a uniform and a relatively low voltage drop for each of its multiple parallel contacts. This is provided by a cathode pole piece which is of a semiconductive material such as silicon which matches the silicon semiconductive material and thus the thermal expansion characteristics of the active part of the semiconductive switching device. In addition, a permanent bond is provided between the cathode pole piece and the multiple contacts by providing suitable metallic contact layers and then by the application of heat and pressure.