Abstract: Lateral MOS controlled gate turn-off triacs with large OFF-Gate-width to emitter-width ratios. In one embodiment an ON channel is provided at one main electrode and an OFF channel is provided at the other. In another embodiment two channels in a series are provided at each main electrode. Current turn-off capacity is increased by serpentine or comb shaped channel regions or by trenches which provide channels along their walls.

Abstract: An improved insulated gate semiconductor device is provided with an extra short grid region of one type conductivity disposed proximate the PN junction between the first and second regions of the device. The extra short grid region provides an alternate path for one type conductivity carriers to inhibit forward biasing of the PN junction between the first and second electrodes. In addition, the grid allows opposite type conductivity carriers to flow therethrough. A portion of the grid is spaced and separated from the first region. Accordingly, a device fabricated in accordance with the present invention is less susceptible to latching and exhibits a higher voltage latching threshold.

Abstract: A semiconductor device comprises four regions of alternating conductivity type and comprises a plurality of turn-on cells at one of its major surfaces and a plurality of turn-off cells at another of its major surfaces. Both the turn-on and turn-off cells are of the conductor-insulator-semiconductor type. In an embodiment, the cell repeat distance for both turn-on cells and turn-off cells is preferably less than about the minimum thickness of the region of the semiconductor device that supports most of the device voltage. This enables the semiconductor device to operate efficiently in a field-effect transistor mode, in addition to a thyristor mode.

Abstract: A method for the discretionary interconnection of plural devices into an array includes the steps of designing bridge sites between the devices, individually testing the devices, inking over the bridge sites to devices which do not meet predetermined parameters, and soldering in a manner to cause the solder to bridge the gap between the acceptable devices and the rest of the array but not to bridge the gap to unacceptable devices. In devices comprised of multiple parallel elements, only sub-elements which fall within predetermined functional requirement ranges are incorporated into the parallel array produced. This method of discretionary interconnection is readily adapted to automated techniques for fabricating semiconductor MOS devices such as MCTs, IGBTs and parallel MOSFET arrays.

Abstract: Insulated-gate semiconductor devices, such as MOSFETs or IGTs, include an implant shorting region adjoining both base and source regions with the implant shorting region being conductively coupled to the source electrode so as to implement a base-to-source electrode short. The implant shorting region can be formed without a specially-aligned mask by utilizing the gate electrode as an implant mask.

Abstract: A thyristor is provided having high gate sensitivity in combination with high dv/dt ratings. An amplifying gate structure is utilized having a pilot thyristor region including a first portion characterized by a first extent and at least one projection of said first portion extending therefrom and having a lateral extent greater than the extent of said first portion; and means substantially isolating said pilot thyristor region from the remainder of the device which means surround said first portion and the sides of said projection.

Abstract: A multiple-zone junction termination extension region is formed adjacent a reverse-blocking junction in a semiconductor device to increase the breakdown voltage of such device. A single mask is used to form the multiple-zone JTE region, with the mask having different patterns of openings in the different zones of the mask. Adjacent openings are maintained with a center-to-center spacing of less than 25 percent of the depletion width of the reverse-blocking junction in a voltage-supporting semiconductor layer adjoining the reverse-blocking junction at the ideal breakdown voltage of the junction. As a consequence, the resulting non-uniformities in doping of the various zones of the JTE region are negligibly small. An alternative JTE region is finely-graduated in dopant level from one end of the region to the other, as opposed to having multiple zones of discrete doping levels.

Abstract: Power semiconductor devices having active regions of multicellular construction achieve increased turn-off current capacity through limitation of the on-state current density in peripheral cells of the active region. Devices that may benefit from the present invention include MOSTOTs, IGTs, GTOs, and bipolar transistors, by way of example.

Abstract: An insulated-gate semiconductor device, such as an IGFET or IGT, with improved source-to-base shorts includes, in a semiconductor wafer, a drain region, a voltage-supporting region, a base region, and a source region. Generally parallel gate fingers of refractory material are insulatingly spaced above the wafer. Elongated base portions are provided between, and preferably registered to, a respective pair of adjacent gate fingers. Elongated source portions are each situated within a respective base portion and each is preferably registered to a respective pair of adjacent gate fingers. Generally parallel shorting portions are included in the wafer and are oriented transverse to the gate fingers, whereby the shorting portions can be formed without a critical alignment step. The shorting portions adjoin the base portions and also a source electrode so as to complete source-to-base electrical shorts.

Abstract: A semiconductor device used for high voltage applications exhibits reduced susceptibility to being inadvertently turned-on by capacitive charging currents generated by relatively high voltage transients impressed across an anode and a cathode of the device. The capacitive charging currents are manifested as a gate current which in a thyristor renders the device conductive if it exceeds a critical value and in a transistor is multiplied by the current gain. Various embodiments employing capacitors are disclosed for reducing the level and/or the duration of the transient produced gate current.

Abstract: Reduction in the forward current gain of an inherent bipolar transistor in an insulated-gate semiconductor device such as an IGT or an IGFET is achieved by implantation of selected ions into the semiconductor material of such device. The ions, which create defects in the implanted region constituting current carrier recombination centers, form a layer with a peak concentration situated in proximity to the emitter-base junction of the inherent bipolar transistor. The layer of ions is of small thickness, whereby the resulting increase in the respective sheet resistances of the emitter and base layers to either side of the emitter-base junction is minimized.

Abstract: Process for manufacturing insulated-gate semiconductor devices such as MOSFETs being with a semiconductor wafer (such as silicon) including a drain region, a gate insulating layer initially formed uniformly on the surface of the drain region, and a polysilicon conductive gate layer. A two-stage polysilicon etch procedure is disclosed. The initial etch produces relatively narrow channels with substantially vertical sidewalls. Unetched portions of the polysilicon layer are used as masks during a first P type diffusion to form a shorting extension of the device base region and during the forming of a silicon nitride mask layer by a highly directional process, such as ion implantation, which avoids the formation of any nitride layer on the channel sidewalls. In a subsequent lateral etch step, previously unetched portions of the polysilicon gate electrode layer are etched to define insulated polysilicon gate electrode structures.

Abstract: Processes for manufacturing insulated-gate semiconductor devices such as MOSFETs wherein the source and base regions and the source-to-base ohmic short are formed employing self-aligned masking techniques are disclosed. In the exemplary case of a MOSFET, the processes begin with a semiconductor wafer (such as silicon) including a drain region, a gate insulating layer initially formed uniformly on the surface of the drain region, and a polysilicon conductive gate layer. Through subsequent masking and etching steps, channels are etched through the polysilicon gate layer at least to the drain region. The un-etched portions define polysilicon gate electrodes spaced along the drain region. A two-stage polysilicon etch procedure is disclosed. An initial etch step produces relatively narrow channels. Unetched portions of the polysilicon layer are then used as masks to form a shorting extension of the device base region, preferably by ion implantation.

Abstract: Processes for manufacturing insulated-gate semiconductor devices characterized by involving a minimal number of photolithographic masking steps and being fail-safe in a number of respects. A number of process alternatives are disclosed for forming a shorting extension of a base region up through and to a portion of the surface of a source region, many of these process alternatives involving self-masking techniques to define the source region surface portion. Two general MOSFET structures are formed in accordance with the procedures of the invention. One structure has metallized gate terminal fingers, and is formed employing one-mask processes. The other structure has gate fingers encased in insulating oxide and connected to remote gate contacts. For both structures, selective oxidation of the polysilicon gate electrode material is preferred, and various approaches to this selective oxidation are described.

Abstract: A precisely formed region of semiconductor material which correspondingly contains a precisely controlled amount of charge when depleted is provided in the proximity of a p-n junction in several kinds of semiconductor devices. This region is located within the selected semiconductor device in such a manner as to increase avalanche breakdown voltage of a p-n junction to near its ideal value and to reduce both peak bulk and peak surface electric fields.

Abstract: A thyristor with a segmented turn-on line is provided in which portions of the turn-on line are covered by boundary shorts formed by the emitter electrode extending over the emitter-base junction into contact with the thyristor base zone. The portions of the emitter-base junction between the boundary shorts constitute turn-on segments along which gated thyristor turn-on can occur. A gate current source is provided for supplying carriers to the base zone. The thyristor includes means for directing carriers supplied by the gate current source to the turn-on segments. In operation, initial thyristor turn-on occurs only along the turn-on segments, thereby shortening the length of the thyristor turn-on line and increasing gate sensitivity. Preferably, the turn-on segments are spaced regularly along the emitter-base junction to permit adjacent "on" areas to rapidly merge.

Abstract: A thyristor having an emitter on the top surface of a semiconductor body and also having metalized areas on the top surface forming electrodes is provided with an alignment region extending beneath the edge of the gate electrode. The alignment region is formed in the thyristor base zone and is of the same conductivity type as the thyristor emitter. Precise spacing between the alignment region and the emitter is readily achieved because both are formed in a single masking step. Slight misalignment of the gate metalization on the top surface is corrected for because the alignment region precisely defines the line closest to the emitter at which the gate electrode contacts the base. The turn-on potential at the emitter-based junction is therefore uniform along its entire length.

Abstract: A thyristor of the type having a localized voltage breakover region is provided with current limiting means for controlling the current through the device during initial voltage breakover. The thyristor base zone is divided into two at least partially separated base portions, one of which is in the vicinity of the localized breakover region. The other base portion is in the main current-carrying part of the thyristor in contact with the main emitter. The two base portions are electrically connected by current limiting means. When breakover occurs by way of a forward anode-cathode voltage which exceeds the thyristor forward breakover voltage, the rise in current is limited by the current limiting means.

Abstract: A semiconductor device which can be turned on at voltage signals applied thereto below a selected voltage magnitude includes a pinch-off region of semiconductor material having a precisely controlled net dopant charge situated in the gate current path of the semiconductor device such that the normal gate current path of the device is pinched-off when the voltage applied to the device equals or exceeds the selected magnitude.

Abstract: A semiconductor device used for high voltage applications exhibits reduced susceptibility to being inadvertently turned-on by capacitive charging currents generated by relatively high voltage transients impressed across an anode and a cathode of the device. The capacitive charging currents are manifested as a gate current which in a thyristor renders the device conductive if it exceeds a critical value and in a transistor is multiplied by the current gain. A conductive ring and adjacent groove are employed on the surface of the device, along with certain interconnections, to maintain the level of the transient-produced gate current at a value below the critical value.