Abstract: A blood glucose meter having a test strip port and an adjustable lancet device disposed at the same end of the device body is disclosed. The device body further includes an enclosure at the proximal end of the device body which houses a test strip storage vial and which facilitates one-handed opening and closing of the vial to simplify access to test strips contained therein. The enclosure is further provided with a window which allows the reading of the lot numbers on the label of the test strip vial therein without necessitating removal of the vial. A data connector is also provided on the device body for communication access, such as to upload data from other devices or to download data to other devices.

Abstract: A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.

Abstract: A telecommunications system includes a network; a plurality of client devices operably coupled to said network, said plurality of client devices adapted to set one or more time contact parameters for buddies on a contact list; and a presence server including a timer, and adapted to maintain a timing of time contacts for selected contacts responsive to said parameters.

Abstract: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.

Abstract: An ankle fusion device has a proximal portion generally aligned with a first longitudinal axis. The proximal portion includes a proximal end and a first fastener hole. The proximal portion has an arcuate curve such that the proximal end is spaced a distance from the first longitudinal axis in a first direction. The first fastener hole is configured to receive a first fastener along a first fastener axis. A distal portion of the ankle fusion device extends to a distal end from the proximal portion along a second longitudinal axis. The second longitudinal axis is angled in second and third directions relative to the first longitudinal axis. The second direction is perpendicular to the first direction and the third direction being opposite the first direction. The distal portion includes a second fastener hole configured to receive a second fastener along a second fastener axis.

Abstract: Generating an embedded resistor in a semiconductor device includes forming a shallow trench isolation (STI) region in a substrate; forming a pad oxide on the STI region and substrate; depositing a silicon layer on the pad oxide; forming a photo-resist mask on a portion of the silicon layer disposed above the STI region; etching the silicon layer to yield a polyconductor above the STI region; oxidizing the polyconductor; depositing an oxide material or a metal gate material on the oxidized surface; depositing a silicon layer on the oxide material or metal gate material; depositing additional silicon on a portion of the silicon layer above the STI region; patterning a transistor gate with a photo-resist mask on another portion of the silicon layer away from the STI region; and etching the silicon layer to yield a transistor structure away from the STI region and a resistor structure above the STI region.

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.

Abstract: A medical regimen can be administered with a diagnostic and medication delivery system. In one form the system includes a medication delivery pen with a controller and a monitor for monitoring a characteristic of a bodily fluid with a controller. A case includes a compartment for removably storing the medication delivery pen and the monitor. The case includes a communications link for establishing communication between the controller of the pen and the controller of the monitor. The medication delivery pen and monitor are operable in a first mode cooperative with one another and in a second mode independent of one another.

Abstract: An apparatus for storing and dispensing a test strip includes a container configured to store a stack of test strips. The container maintains appropriate environmental conditions, such as humidity, for storing the test strips. An engaging member is disposed in the container and is adapted to contact one test strip of the stack of test strips. An actuator actuates the engaging member to dispense the one test strip from the container. Since one test strip is dispensed at a time, the remaining test strips are not handled by the user. Accordingly, the unused test strips remain free of contaminants such as naturally occurring oils on the user's hand.

Abstract: An apparatus for storing and dispensing a test strip includes a container configured to store a stack of test strips. The container maintains appropriate environmental conditions, such as humidity, for storing the test strips. An engaging member is disposed in the container and is adapted to contact one test strip of the stack of test strips. An actuator actuates the engaging member to dispense the one test strip from the container. Since one test strip is dispensed at a time, the remaining test strips are not handled by the user. Accordingly, the unused test strips remain free of contaminants such as naturally occurring oils on the user's hand.

Abstract: An electrical power extension cord having a male plug end, a female receptacle end, and an insulated flexible cordset extending between the male and female ends of the extension cord. The male end has a first prong electrically connected to a hot wire contained in the cordset, a second prong electrically connected to a neutral wire in the cordset, and a third prong electrically connected to a ground wire in the cordset. The female end has a first receptacle electrically connected to a hot wire contained in the cordset, a second receptacle electrically connected to the neutral wire in the cordset, and a third receptacle electrically connected to the ground wire in the cordset. Continuous electrical current and ground monitoring circuits are contained in the male and female ends of the extension cord.

Abstract: Methods of characterizing a mechanical stress level in a stressed layer of a transistor and a mechanical stress characterizing test structure are disclosed. In one embodiment, the test structure includes a first test transistor including a first stress level; and at least one second test transistor having a substantially different second stress level. A testing circuit can then be used to characterize the mechanical stress level by comparing performance of the first test transistor and the at least one second test transistor. The type of test structure depends on the integration scheme used. In one embodiment, at least one second test transistor is provided with a substantially neutral stress level and/or an opposite stress level from the first stress level. The substantially neutral stress level may be provided by either rotating the transistor, removing the stressed layer causing the stress level or de-stressing the stressed layer causing the stress layer.

Abstract: A method includes associating an e-mail address with a plurality of telephone numbers; associating one of the telephone numbers with a one number service (108); allowing telephone calls to the one of the telephone numbers by selecting the e-mail address. In some embodiments, the allowing telephone calls comprises calling a programmed caller number and calling to a called party number associated with the e-mail address. In some embodiments, a called party and a calling party are subscribers to a one-number service (108).

Abstract: A system and method for handling multiple identical requests received by a server from a client by a web application server. When multiple requests for the same URL are received by a web application server from the same client browser which results in the allocation of multiple threads on the server to handle the requests, a response to the client is obtained from the processing carried out by the first thread launched by the web application server. Results of the initial thread are passed to the client using the last opened connection between the client and server relating to the client's request for the URL. Other threads are placed in a wait state and are deallocated, at the earliest opportunity, where possible.

Abstract: A method for generating an embedded resistor in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including forming a shallow trench isolation (STI) region in a substrate; forming a pad oxide on the STI region and substrate; depositing a silicon layer on the pad oxide; forming a photo-resist mask on a portion of the silicon layer disposed substantially above the STI region.

Abstract: A system and method for enabling the e-commerce purchasing of grouped merchandise and/or services, known as packages, is disclosed. The subject e-commerce system and method comprises a catalog database comprising package data correlated to at least one package; a selection module coupled to the catalog database for allowing a customer to select a package for purchase; and a resolution module coupled to the catalog database for resolving unresolved attributes in the selected package. Preferably, the catalog database further comprises item data correlated to a plurality of items, wherein each item is fully resolved; product data correlated to at least one product, wherein said at least one product comprises at least one unresolved attribute; and attribute data.

Abstract: A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.

Abstract: A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.

Abstract: A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.

Abstract: A medical regimen can be administered with a diagnostic and medication delivery system. In one form the system includes a medication delivery pen with a controller and a monitor for monitoring a characteristic of a bodily fluid with a controller. A case includes a compartment for removably storing the medication delivery pen and the monitor. The case includes a communications link for establishing communication between the controller of the pen and the controller of the monitor. The medication delivery pen and monitor are operable in a first mode cooperative with one another and in a second mode independent of one another.