Patents by Inventor Vijay Narayanan

Vijay Narayanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ADVANCED MOSFET CONTACT STRUCTURE TO REDUCE METAL-SEMICONDUCTOR INTERFACE RESISTANCE
    Publication number: 20170133265
    Abstract: A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at least one of the source region and the drain region, the source/drain contact including a conductive metal and a bilayer disposed between the conductive metal and the at least one of the source and drain region, the bilayer including a metal oxide layer in contact with the conductive metal, and a silicon dioxide layer in contact with the at least one of the source and drain region.
    Type: Application
    Filed: January 27, 2017
    Publication date: May 11, 2017
    Inventors: Huiming Bu, Hui-feng Li, Vijay Narayanan, Hiroaki Niimi, Tenko Yamashita
  • Tailored silicon layers for transistor multi-gate control
    Patent number: 9646886
    Abstract: Disclosed is a process of making field-effect transistor gate stacks containing different deposited thin film silicon material layers having different hydrogen content, and devices comprising these gate stacks. The threshold voltage (Vt) can be tuned by tailoring the hydrogen content of the thin film silicon material layer positioned below a core dielectric and directly on a semiconductor material substrate.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: May 9, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vijay Narayanan, John Rozen
  • Tailored silicon layers for transistor multi-gate control
    Patent number: 9646887
    Abstract: Disclosed is a process of making field-effect transistor gate stacks containing different deposited thin film silicon material layers having different hydrogen content, and devices comprising these gate stacks. The threshold voltage (Vt) can be tuned by tailoring the hydrogen content of the thin film silicon material layer positioned below a core dielectric and directly on a semiconductor material substrate.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: May 9, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vijay Narayanan, John Rozen
  • Method to improve reliability of high-K metal gate stacks
    Patent number: 9634116
    Abstract: A method of fabricating a gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over an area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; annealing the replacement gate structure in an ambient atmosphere containing hydrogen; and depositing a gap fill layer.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: April 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Eduard A. Cartier, Barry P. Linder, Vijay Narayanan
  • EXPITAXIALLY REGROWN HETEROSTRUCTURE NANOWIRE LATERAL TUNNEL FIELD EFFECT TRANSISTOR
    Publication number: 20170110539
    Abstract: After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.
    Type: Application
    Filed: October 20, 2015
    Publication date: April 20, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan, Jeffrey W. Sleight
  • Replacement channel TFET
    Patent number: 9627508
    Abstract: A semiconductor structure includes a substrate and an intrinsic replacement channel. A tunneling field effect transistor (TFET) fin may be formed by the intrinsic replacement channel, a p-fin and an n-fin formed upon the substrate. The p-fin may serve as the source of the TFET and the n-fin may serve as the drain of the TFET. The replacement channel may be formed in place of a sacrificial channel of a diode fin that includes the p-fin, the n-fin, and the sacrificial channel at the p-fin and n-fin junction.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: April 18, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Michael P. Chudzik, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan, Jeffrey W. Sleight
  • ACTIVATED THIN SILICON LAYERS
    Publication number: 20170092725
    Abstract: A method for forming a layer of material on a silicon layer comprises depositing a layer of silicon material having a hydrophobic H-terminated surface on a substrate, forming a hydrophilic seed layer on the surface of the silicon material, and depositing an oxide material layer on the hydrophilic seed layer.
    Type: Application
    Filed: September 29, 2015
    Publication date: March 30, 2017
    Inventors: Takashi Ando, Martin M. Frank, Vijay Narayanan, John Rozen
  • ACTIVATED THIN SILICON LAYERS
    Publication number: 20170092501
    Abstract: A method for forming a layer of material on a silicon layer comprises depositing a layer of silicon material having a hydrophobic H-terminated surface on a substrate, forming a hydrophilic seed layer on the surface of the silicon material, and depositing an oxide material layer on the hydrophilic seed layer.
    Type: Application
    Filed: December 8, 2015
    Publication date: March 30, 2017
    Inventors: Takashi Ando, Martin M. Frank, Vijay Narayanan, John Rozen
  • HIGH-K SPACER FOR EXTENSION-FREE CMOS DEVICES WITH HIGH MOBILITY CHANNEL MATERIALS
    Publication number: 20170092723
    Abstract: A field effect transistor device includes a gate structure formed over a channel region in a semiconductor material. An inner spacer is formed on sidewalls of the gate structure and over an extension region of the semiconductor material. The inner spacer includes charge or dipoles. A source/drain region is formed adjacent to the gate structure. An inversion layer is formed in the extension region induced by the inner spacer to form a conductive link between the channel region and the source/drain region.
    Type: Application
    Filed: September 29, 2015
    Publication date: March 30, 2017
    Inventors: Takashi Ando, Pouya Hashemi, Vijay Narayanan, Yanning Sun
  • High-K spacer for extension-free CMOS devices with high mobility channel materials
    Patent number: 9608066
    Abstract: A field effect transistor device includes a gate structure formed over a channel region in a semiconductor material. An inner spacer is formed on sidewalls of the gate structure and over an extension region of the semiconductor material. The inner spacer includes charge or dipoles. A source/drain region is formed adjacent to the gate structure. An inversion layer is formed in the extension region induced by the inner spacer to form a conductive link between the channel region and the source/drain region.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Pouya Hashemi, Vijay Narayanan, Yanning Sun
  • Dipole-based contact structure to reduce metal-semiconductor contact resistance in MOSFETs
    Patent number: 9589851
    Abstract: A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at least one of the source region and the drain region, the source/drain contact including a conductive metal and a bilayer disposed between the conductive metal and the at least one of the source and drain region, the bilayer including a metal oxide layer in contact with the conductive metal, and a silicon dioxide layer in contact with the at least one of the source and drain region.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: March 7, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., THE RESEARCH FOUNDATION FOR THE STATE UNIVERSITY OF NEW YORK
    Inventors: Huiming Bu, Hui-feng Li, Vijay Narayanan, Hiroaki Niimi, Tenko Yamashita
  • Semiconductor devices containing an epitaxial perovskite/doped strontium titanate structure
    Patent number: 9590100
    Abstract: Semiconductor devices are provided such as, ferroelectric transistors and floating gate transistors, that include an epitaxial perovskite/doped strontium titanate structure formed above a surface of a semiconductor substrate. The epitaxial perovskite/doped strontium titanate structure includes a stack of, in any order, a doped strontium titanate and a perovskite type oxide.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: March 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Catherine A. Dubourdieu, Martin M. Frank, Vijay Narayanan
  • Gate stack with tunable work function
    Patent number: 9583400
    Abstract: A method for fabricating a gate stack of a semiconductor device comprising forming a first dielectric layer over a channel region of the device, forming a barrier layer over the first dielectric layer, forming a first gate metal layer over the barrier layer, forming a capping layer over the first gate metal layer, removing portions of the barrier layer, the first gate metal layer, and the capping layer to expose a portion of the first dielectric layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a first nitride layer on exposed portions of the capping layer and the first dielectric layer, depositing a scavenging layer on the first nitride layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: February 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • HIGH-K GATE DIELECTRIC AND METAL GATE CONDUCTOR STACK FOR FIN-TYPE FIELD EFFECT TRANSISTORS FORMED ON TYPE III-V SEMICONDUCTOR MATERIAL AND SILICON GERMANIUM SEMICONDUCTOR MATERIAL
    Publication number: 20170053915
    Abstract: An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.
    Type: Application
    Filed: August 17, 2015
    Publication date: February 23, 2017
    Inventors: Takashi Ando, Martin M. Frank, Pranita Kerber, Vijay Narayanan
  • Changing effective work function using ion implantation during dual work function metal gate integration
    Patent number: 9564505
    Abstract: Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: February 7, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Michael P. Chudzik, Martin M. Frank, Herbert L. Ho, Mark J. Hurley, Rashmi Jha, Naim Moumen, Vijay Narayanan, Dae-Gyu Park, Vamsi K. Paruchuri
  • Semiconductor device having a gate stack with tunable work function
    Patent number: 9559016
    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer and the scavenging layer to expose a portion of the first nitride layer in a n-type field effect transistor (nFET) region of the gate stack, forming a first gate metal layer over the first nitride layer and the capping layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: January 31, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Dipole-Based Contact Structure to Reduce Metal-Semiconductor Contact Resistance in MOSFETs
    Publication number: 20170018463
    Abstract: A transistor device includes a substrate; a source region and a drain region formed over the substrate; and a source/drain contact formed in contact with at least one of the source region and the drain region, the source/drain contact including a conductive metal and a bilayer disposed between the conductive metal and the at least one of the source and drain region, the bilayer including a metal oxide layer in contact with the conductive metal, and a silicon dioxide layer in contact with the at least one of the source and drain region.
    Type: Application
    Filed: July 16, 2015
    Publication date: January 19, 2017
    Inventors: Huiming Bu, Hui-feng Li, Vijay Narayanan, Hiroaki Niimi, Tenko Yamashita
  • Method and structure for III-V nanowire tunnel FETs
    Patent number: 9548381
    Abstract: A heterojunction tunnel field effect transistor (TFET) has a channel region that includes a first portion of a nanowire, a source region and a drain region that respectively include a second portion and a third portion of a nanowire, and a gate that surrounds the channel region, where the first portion of the nanowire comprises an intrinsic, epitaxial III-V semiconductor. The TFET can be made by selectively etching the epitaxial underlayer to define a tethered (suspended) nanowire that forms a channel region of the device. Source and drain regions can be formed from regrown p-type and n-type epitaxial layers.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: January 17, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan, Jeffrey W. Sleight
  • METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE
    Publication number: 20170005179
    Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.
    Type: Application
    Filed: September 16, 2016
    Publication date: January 5, 2017
    Inventors: TAKASHI ANDO, EDUARD A. CARTIER, KISIK CHOI, VIJAY NARAYANAN
  • METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE
    Publication number: 20160380076
    Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.
    Type: Application
    Filed: September 7, 2016
    Publication date: December 29, 2016
    Inventors: Takashi Ando, Eduard A. Cartier, Kisik Choi, Vijay Narayanan