Patents by Inventor Vijay Narayanan

Vijay Narayanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Trench metal insulator metal capacitor with oxygen gettering layer
    Patent number: 9911597
    Abstract: A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Eduard A. Cartier, Michael P. Chudzik, Aritra Dasgupta, Herbert L. Ho, Donghun Kang, Rishikesh Krishnan, Vijay Narayanan, Kern Rim
  • Integrated metal gate CMOS devices
    Patent number: 9899264
    Abstract: A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Dechao Guo, Vijay Narayanan
  • FIELD EFFECT TRANSISTOR STACK WITH TUNABLE WORK FUNCTION
    Publication number: 20180047639
    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.
    Type: Application
    Filed: October 27, 2017
    Publication date: February 15, 2018
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • FIELD EFFECT TRANSISTOR STACK WITH TUNABLE WORK FUNCTION
    Publication number: 20180047640
    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.
    Type: Application
    Filed: October 27, 2017
    Publication date: February 15, 2018
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • BINARY METAL OXIDE BASED INTERLAYER FOR HIGH MOBILITY CHANNELS
    Publication number: 20180040708
    Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.
    Type: Application
    Filed: August 4, 2016
    Publication date: February 8, 2018
    Inventors: Vijay Narayanan, Yohei Ogawa, John Rozen
  • BINARY METAL OXIDE BASED INTERLAYER FOR HIGH MOBILITY CHANNELS
    Publication number: 20180040709
    Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.
    Type: Application
    Filed: August 23, 2017
    Publication date: February 8, 2018
    Inventors: Vijay Narayanan, Yohei Ogawa, John Rozen
  • BINARY METAL OXIDE BASED INTERLAYER FOR HIGH MOBILITY CHANNELS
    Publication number: 20180040710
    Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.
    Type: Application
    Filed: August 23, 2017
    Publication date: February 8, 2018
    Inventors: Vijay Narayanan, Yohei Ogawa, John Rozen
  • TAPERED METAL NITRIDE STRUCTURE
    Publication number: 20180019299
    Abstract: A tapered metal nitride structure having a gentle sloping (i.e., tapered) sidewall is provided that includes an oxygen rich metal nitride portion located between each metal nitride portion of a stack of metal nitride portions. The structure is formed by incorporating/introducing oxygen into an upper portion of a first metal nitride layer to form an oxygen rich metal nitride surface layer. A second nitride is then formed atop the oxygen rich metal nitride surface layer. The steps of oxygen incorporation/addition and nitride layer formation may be repeated any number of times. An etch mask is then provided and thereafter a sputter etch is performed to provide the tapered metal nitride structure. The tapered metal nitride structure may be used as an electrode in a semiconductor device.
    Type: Application
    Filed: July 18, 2016
    Publication date: January 18, 2018
    Inventors: Martin M. Frank, Hiroyuki Miyazoe, Vijay Narayanan
  • INTEGRATED METAL GATE CMOS DEVICES
    Publication number: 20180005891
    Abstract: A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Ruqiang Bao, Dechao Guo, Vijay Narayanan
  • COMBINED REACTIVE GAS SPECIES FOR HIGH-MOBILITY CHANNEL PASSIVATION
    Publication number: 20180005821
    Abstract: A technique relates to in-situ cleaning of a high-mobility substrate. Alternating pulses of a metal precursor and exposure to a plasma of a gas or gas mixture are applied. The gas or gas mixture contains both nitrogen and hydrogen (e.g., NH3). A passivation layer is formed on the high-mobility substrate by alternating pulses of the metal precursor and exposure to the plasma of a gas, or gas mixture, containing both nitrogen and hydrogen.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Takashi Ando, Vijay Narayanan, Yohei Ogawa, John Rozen
  • INTEGRATED METAL GATE CMOS DEVICES
    Publication number: 20180006033
    Abstract: A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.
    Type: Application
    Filed: April 28, 2017
    Publication date: January 4, 2018
    Inventors: Ruqiang Bao, Dechao Guo, Vijay Narayanan
  • STACKED CAPACITOR WITH SYMMETRIC LEAKAGE AND BREAK-DOWN BEHAVIORS
    Publication number: 20180006108
    Abstract: A layered structure including a tri-stack dielectric layer and a plurality of metal layers insulated from each other by the tri-stack dielectric layer. The plurality of metal layers includes a set of first-type metal layers and a set of second-type metal layers. An adjacent pair of the plurality of metal layers includes a first-type metal layer and a second-type metal layer. The tri-stack dielectric layer includes a first tri-stack layer including Al2O3, a second tri-stack layer including HfO2; and a third tri-stack layer including Al2O3.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Takashi Ando, Eduard A. Cartier, Vijay Narayanan, Adam M. Pyzyna
  • Field effect transistor stack with tunable work function
    Patent number: 9859169
    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • High-k gate dielectric and metal gate conductor stack for fin-type field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material
    Patent number: 9859279
    Abstract: An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Martin M. Frank, Pranita Kerber, Vijay Narayanan
  • SHARED METAL GATE STACK WITH TUNABLE WORK FUNCTION
    Publication number: 20170358655
    Abstract: Semiconductor devices and methods of forming the same include forming a work function stack over semiconductor fins in a first region and a second region, the work function stack having a bottom layer, a middle layer, and a top layer. The work function stack is etched to remove the top layer and to decrease a thickness of the middle layer in the second region, leaving a portion of the middle layer and the bottom layer intact. A gate is formed over the semiconductor fins in the first and second regions.
    Type: Application
    Filed: June 8, 2016
    Publication date: December 14, 2017
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • PROCESS FOR THE PREPARATION OF 1-(2,6,6-TRIMETHYLCYCLOHEXYL)-ALKAN-3-OLS
    Publication number: 20170355670
    Abstract: The present invention relates to a process for the preparation of 1-(2,6,6-trimethylcyclohexylyalkan-3-ols, in particular 1-(2,6,6-trimethylcyclohexyl)-hexan-3-ol. The invention further relates to 5-alkoxy-1-(2,6,6-trimethylcyclohexenyl)-1-alken-3-ones and the use of these as a fragrance or as flavor, to a fragrance containing composition and/or a fragranced product containing 5-alkoxy-1-(2,6,6-trimethylcyclohexenyl)-1-alken-3-ones and to a method for imparting or modifying a scent or a flavor to a composition by including said alkoxyalkenones into such composition.
    Type: Application
    Filed: November 17, 2015
    Publication date: December 14, 2017
    Inventors: Stefan RÜDENAUER, Ralf PELZER, Miriam BRU ROIG, Vijay Narayanan SWAMINATHAN, Shrirang HINDALEKAR, Nitin GUPTE, Prachin KOLAMBKAR
  • HIGH-K GATE DIELECTRIC AND METAL GATE CONDUCTOR STACK FOR FIN-TYPE FIELD EFFECT TRANSISTORS FORMED ON TYPE III-V SEMICONDUCTOR MATERIAL AND SILICON GERMANIUM SEMICONDUCTOR MATERIAL
    Publication number: 20170358579
    Abstract: An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.
    Type: Application
    Filed: August 8, 2017
    Publication date: December 14, 2017
    Inventors: Takashi Ando, Martin M. Frank, Pranita Kerber, Vijay Narayanan
  • PROTECTION OF HIGH-K DIELECTRIC DURING RELIABILITY ANNEAL ON NANOSHEET STRUCTURES
    Publication number: 20170323949
    Abstract: A starting structure for forming a gate-all-around field effect transistor (FET) and a method of fabricating the gate-all-around FET. The method includes forming a stack of silicon nanosheets above a substrateforming an interfacial layer over the nanosheets depositing a high-k dielectric layer conformally on the interfacial layer. The method also includes depositing a layer of silicon nitride (SiN) above the high-k dielectric layer and performing reliability anneal after depositing the layer of SiN to crystallize the high-k dielectric layer.
    Type: Application
    Filed: May 4, 2016
    Publication date: November 9, 2017
    Inventors: Nicolas J. Loubet, Sanjay C. Mehta, Vijay Narayanan, Muthumanickam Sankarapandian
  • DISTINCT GATE STACKS FOR III-V-BASED CMOS CIRCUITS COMPRISING A CHANNEL CAP
    Publication number: 20170316979
    Abstract: Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.
    Type: Application
    Filed: July 13, 2017
    Publication date: November 2, 2017
    Inventors: Takashi Ando, Martin M. Frank, Renee T. Mo, Vijay Narayanan
  • STRUCTURES AND METHODS FOR EQUIVALENT OXIDE THICKNESS SCALING ON SILICON GERMANIUM CHANNEL OR III-V CHANNEL OF SEMICONDUCTOR DEVICE
    Publication number: 20170309723
    Abstract: A method of forming a semiconductor device that includes forming a metal oxide material on a III-V semiconductor channel region or a germanium containing channel region; and treating the metal oxide material with an oxidation process. The method may further include depositing of a hafnium containing oxide on the metal oxide material after the oxidation process, and forming a gate conductor atop the hafnium containing oxide. The source and drain regions are on present on opposing sides of the gate structure including the metal oxide material, the hafnium containing oxide and the gate conductor.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 26, 2017
    Inventors: Takashi Ando, John Bruley, Eduard A. Cartier, Martin M. Frank, Vijay Narayanan, John Rozen