Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

Abstract: A semiconductor structure includes a substrate and an intrinsic replacement channel. A tunneling field effect transistor (TFET) fin may be formed by the intrinsic replacement channel, a p-fin and an n-fin formed upon the substrate. The p-fin may serve as the source of the TFET and the n-fin may serve as the drain of the TFET. The replacement channel may be formed in place of a sacrificial channel of a diode fin that includes the p-fin, the n-fin, and the sacrificial channel at the p-fin and n-fin junction.

Abstract: An electrical device that includes a substrate including a first region of a type III-V semiconductor material and a second region of a type IV germanium containing semiconductor material. An n-type planar FET is present in the first region of the substrate. A p-type planar FET is present in a second region of the substrate. A gate structure for each of the n-type planar FET and the p-type planar FET includes a metal containing layer including at least one of titanium and aluminum atop a high-k gate dielectric. An effective work function of the gate structure for both the n-type and p-type planar FETs is a less than a mid gap of silicon.

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

Abstract: A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. A dummy gate structure may be formed over the high-k dielectric and etched to form an opening over the NMOS region and an opening over the PMOS region. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings.

Abstract: A method of forming a transistor device includes forming an interfacial layer and a dielectric layer over a substrate; and forming a workfunction metal layer over the dielectric layer, the workfunction metal layer comprising a titanium-aluminum-carbon-oxygen (TiAlCO) layer.

Abstract: A technique relates to forming a transistor. A dummy gate is formed on a substrate with spacers on both sides. A source and a drain are formed in the substrate, where the source and the drain are positioned under the spacers. An interlayer dielectric is formed on top of the substrate, the spacers, and the dummy gate. The interlayer dielectric is planarized along with part of the spacers and the dummy gate. The dummy gate is removed, thereby leaving an opening. A sacrificial layer is deposited on top of the substrate in a bottom of the opening. The sacrificial layer includes at least one of silicon germanium and/or germanium. The sacrificial layer is removed from the substrate in the bottom of the opening, thereby growing an interfacial oxide layer on the substrate in the opening. A high-? dielectric layer is deposited on top of the interfacial oxide layer.

Abstract: A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate dielectric, a planar high-k gate dielectric, a metallic nitride portion, and a first semiconductor material portion, and the second gate structure includes a silicon-based dielectric material portion and a second semiconductor material portion. After formation of gate spacers and a planarization dielectric layer, the second gate structure is replaced with a transient gate structure including a chemical oxide portion and a second high-k gate dielectric. A work-function metal layer and a conductive material portion can be formed in each gate electrode by replacement of semiconductor material portions. A gate electrode includes the planar silicon-based gate dielectric, the planar high-k gate dielectric, and a U-shaped high-k gate dielectric, and another gate electrode includes the chemical oxide portion and another U-shaped high-k gate dielectric.

Abstract: The disclosure generally relates to a method for forming multiple III-V Tunnel Field-Effect Transistors (III-V TFETs) microchips in which each TFET has a different threshold voltage (Vt) or work-function. In one embodiment of the disclosure, four TFETs are formed on a substrate. Each TFET has a source, drain and a gate electrode. Each gate electrode is then processed independently to provide a substantially different threshold voltage. Each TFET will have an intrinsic channel.

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

Abstract: A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.

Abstract: A method of fabricating a gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over an area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; annealing the replacement gate structure in an ambient atmosphere containing hydrogen; and depositing a gap fill layer.

Abstract: After removal of the disposable gate structures to form gate cavities in a planarization dielectric layer, a silicon oxide layer is conformally deposited on silicon-oxide-based gate dielectric portions in the gate cavities. A portion of the silicon oxide layer can be nitridated to form a silicon oxynitride layer. A patterned masking material layer can be employed to physically expose a semiconductor surface from a first-type gate cavity. The silicon oxide layer can be removed while preserving an underlying silicon-oxide-based gate dielectric portion in a second-type gate cavity. A stack of a silicon oxynitride layer and an underlying silicon-oxide-based gate dielectric can be protected by a patterned masking material layer in a third-type gate cavity during removal of the silicon oxide layer in the second-type gate cavity. A high dielectric constant gate dielectric layer can be formed in the gate cavities to provide gate dielectrics of different types.

Abstract: A method of forming a transistor device includes forming an interfacial layer and a dielectric layer over a substrate; and forming a workfunction metal layer over the dielectric layer, the workfunction metal layer comprising a titanium-aluminum-carbon-oxygen (TiAlCO) layer.

Abstract: An electrical device that includes a substrate including a first region of a type III-V semiconductor material and a second region of a type IV germanium containing semiconductor material. An n-type planar FET is present in the first region of the substrate. A p-type planar FET is present in a second region of the substrate. A gate structure for each of the n-type planar FET and the p-type planar FET includes a metal containing layer including at least one of titanium and aluminum atop a high-k gate dielectric. An effective work function of the gate structure for both the n-type and p-type planar FETs is a less than a mid gap of silicon.

Abstract: A machine learning model deployment tool can receive a trained machine learning model and driven by a series of user interfaces and by received user input from the user interfaces, can automatically generate machine learning model software and deploy it to a hosting environment. The deployment of a machine learning model can be automated so that custom code does not have to be written by a human. Deployment can be to a single computing device, to a small scale service, to a small scale web service or to “the cloud”, e.g., as a high-scale, fault-tolerant web service utilizing hundreds of computers. Deployment can be guided by a series of user interfaces.

Abstract: A technique relates to forming a transistor. A dummy gate is formed on a substrate with spacers on both sides. A source and a drain are formed in the substrate, where the source and the drain are positioned under the spacers. An interlayer dielectric is formed on top of the substrate, the spacers, and the dummy gate. The interlayer dielectric is planarized along with part of the spacers and the dummy gate. The dummy gate is removed, thereby leaving an opening. A sacrificial layer is deposited on top of the substrate in a bottom of the opening. The sacrificial layer includes at least one of silicon germanium and/or germanium. The sacrificial layer is removed from the substrate in the bottom of the opening, thereby growing an interfacial oxide layer on the substrate in the opening. A high-? dielectric layer is deposited on top of the interfacial oxide layer.

Abstract: Semiconductor devices are provided such as, ferroelectric transistors and floating gate transistors, that include an epitaxial perovskite/doped strontium titanate structure formed above a surface of a semiconductor substrate. The epitaxial perovskite/doped strontium titanate structure includes a stack of, in any order, a doped strontium titanate and a perovskite type oxide.

Abstract: A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. A dummy gate structure may be formed over the high-k dielectric and etched to form an opening over the NMOS region and an opening over the PMOS region. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings.