Abstract: Systems, apparatuses, and methods related to storage device operation orchestration are described. A plurality of computing devices (or “tiles”) can be coupled to a controller (e.g., an “orchestration controller”) and an interface. The controller can control operation of the computing devices. For instance, the controller can include circuitry to request a block of data from a memory device coupled to the apparatus, cause a processing unit of at least one computing device of the plurality of computing devices to perform an operation on the block of data in which at least some of the data is ordered, reordered, removed, or discarded, and cause, after some of the data is ordered, reordered, removed, or discarded, the block of data to be transferred to the interface coupled to the plurality of computing devices.

Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example method can include receiving, at a processing unit that is coupled between a host device and a non-volatile memory device, signaling indicative of a plurality of operations to be performed on data written to or read from the non-volatile memory device. The method can further include performing, at the processing unit, at least one operation of the plurality of operations in response to the signaling. The method can further include accessing a portion of a memory array in the non-volatile memory device. The method can further include transmitting additional signaling indicative of a command to perform one or more additional operations of the plurality of operations on the data written to or read from the non-volatile memory device.

Abstract: Systems, apparatuses, and methods related to bit string accumulation are described. A method for bit string accumulation can include performing an iteration of a recursive operation using a first bit string and a second bit string and modifying a quantity of bits of a result of the iteration of the recursive operation, wherein the modified quantity of bits is less than a threshold quantity of bits. The method can further include writing a first value comprising the modified bits indicative of the result of the iteration of the recursive operation to a first register and writing a second value indicative of the factor corresponding to the result of the iteration of the recursive operation to a second register.

Abstract: A method related to posit tensor processing can include receiving, by a plurality of multiply-accumulator (MAC) units coupled to one another, a plurality of universal number (unum) or posit bit strings organized in a matrix and to be used as operands in a plurality of respective recursive operations performed using the plurality of MAC units and performing, using the MAC units, the plurality of respective recursive operations. Iterations of the respective recursive operations are performed using at least one bit string that is a same bit string as was used in a preceding iteration of the respective recursive operations. The method can further include prior to receiving the plurality of unum or posit bit strings, performing an operation to organize the plurality of unum or posit bit strings to achieve a threshold bandwidth ratio, a threshold latency, or both during performance of the plurality of respective recursive operations.

Abstract: A method includes receiving, by a processing unit coupled to a first memory device comprising a first type of media and a second memory device comprising a second type of media, data captured from an imaging device coupled to the processing unit and determining, by the processing unit, characteristics of a workload corresponding to processing of the data. The method further includes writing, by the processing unit, a portion of data associated with the workload to the other of the first memory device or the second memory device based on the determined characteristics of the workload and causing the workload to be executed while at least the portion of the data associated with the workload is written to the other of the first memory device or the second memory device.

Abstract: A method for blood flow imaging can include receiving, by a processor coupled to a first memory device comprising a first type of media and a second memory device comprising a second type of media, an indication corresponding to initiation of an application and data captured by an imaging device coupled to the processor. The method can include determining characteristics of a workload corresponding to execution of the application to process the data captured by the imaging device for the first memory device and the second memory device and writing the data captured by the imaging device to the first memory device or the second memory device based on determined characteristics for the first memory device and the second memory device in executing the workload.

Abstract: Systems, apparatuses, and methods related to arithmetic and logical operations in a multi-user network are described. Circuitry may be part of a pool of shared computing resources in a multi-user network. Data (e.g., one or more bit strings) received by the circuitry may be selectively operated upon. The circuitry can perform operations on data to convert the data between one or more formats, such as floating-point and/or universal number (e.g., posit) formats and can further perform arithmetic and/or logical operations on the converted data. For instance, the circuitry may be configured to receive a request to perform an arithmetic operation and/or a logical operation using at least one posit bit string operand. The request can include a parameter corresponding to performance of the operation. The circuitry can perform the arithmetic operation and/or the logical operation based, at least in part, on the parameter.

Abstract: Systems, apparatuses, and methods related to acceleration circuitry for posit operations are described. A first operand formatted in a universal number or posit format can be received by a first buffer resident on acceleration circuitry. A second operand formatted in a universal number or posit format can be received by a second buffer resident on the acceleration circuitry. An arithmetic operation, a logical operation, or both can be performed using processing circuitry resident on the acceleration circuitry using the first operand and the second operand. A result of the arithmetic operation, the logical operation, or both can be received by a third buffer resident on the acceleration circuitry.

Abstract: Systems, apparatuses, and methods related to acceleration circuitry for posit operations are described. Signaling indicative of performance of an operation to write a first bit string to a first buffer resident on acceleration circuitry and a second bit string resident on the acceleration circuitry can be received at an DMA controller couplable to the acceleration circuitry. The acceleration circuitry can be configured to perform arithmetic operations, logical operations, or both on bit strings formatted in a unum or posit format. Signaling indicative of an arithmetic operation, a logical operation, or both, to be performed using the first and second bit strings can be transmitted to the acceleration circuitry. The arithmetic operation, the logical operation, or both can be performed via the acceleration circuitry and according to the signaling. Signaling indicative of a result of the arithmetic operation, the logical operation, or both can be transmitting to the DMA controller.

Abstract: Systems, apparatuses, and methods related to bit string operations using a computing tile are described. An example apparatus includes computing device (or “tile”) that includes a processing unit and a memory resource configured as a cache for the processing unit. A data structure can be coupled to the computing device. The data structure can be configured to receive a bit string that represents a result of an arithmetic operation, a logical operation, or both and store the bit string that represents the result of the arithmetic operation, the logical operation, or both. The bit string can be formatted in a format different than a floating-point format.

Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example method can include receiving, at a processing unit that is coupled between a host device and a non-volatile memory device, signaling indicative of a plurality of operations to be performed on data written to or read from the non-volatile memory device. The method can further include performing, at the processing unit, at least one operation of the plurality of operations in response to the signaling. The method can further include accessing a portion of a memory array in the non-volatile memory device. The method can further include transmitting additional signaling indicative of a command to perform one or more additional operations of the plurality of operations on the data written to or read from the non-volatile memory device.

Abstract: Methods, Systems, and Apparatuses related to application-based data type selection are described. A processing device perform operations to monitor performance characteristics associated with various applications executed by a host computing device to determine that a threshold performance level has been reached or exceeded. Operations to convert a data type utilized by the various applications from a first format that supports arithmetic operations to a first level of precision to a second format that supports arithmetic operations to a second level of precision can be performed based, at least in part, on the determination.

Abstract: Memory access control, as described herein, can leverage persistent memory to store data that is generally stored in a non-persistent memory. An example method for memory access control can include receiving, by control circuitry resident on a memory device, a memory access request targeting an address of a volatile (e.g., non-persistent) memory component of the memory device and determining characteristics of data associated with the targeted address. The method can further include accessing data at the targeted address of the volatile memory component in response to determining that the characteristics of the data meet a first criterion and accessing data at another address of a non-volatile memory component in response to determining that the characteristics of the data meet a second criterion.

Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example method includes initiating a read request associated with an address from an input/output device, redirecting the read request to a hierarchical memory component, generating, by the hierarchical memory component, an interrupt message to send to a hypervisor, gathering, at the hypervisor, address register access information from the hierarchical memory component, and determining a physical location of data associated with the read request.

Abstract: Systems, apparatuses, and methods related to dynamic precision bit string accumulation are described. Dynamic bit string accumulation can be performed using an edge computing device. In an example method, dynamic precision bit string accumulation can include performing an iteration of a recursive operation using a first bit string and a second bit string and determining that a result of the iteration of the recursive operation contains a quantity of bits in a particular bit sub-set of the result that is greater than a threshold quantity of bits associated with the particular bit sub-set. The method can further include writing a result of the iteration of the recursive operation to a first register and writing at least a portion of the bits associated with the particular bit sub-set of the result to a second register.

Abstract: Systems, apparatuses, and methods related to storage device operation orchestration are described. A plurality of computing devices (or “tiles”) can be coupled to a controller (e.g., an “orchestration controller”) and an interface. The controller can control operation of the computing devices. For instance, the controller can include circuitry to request a block of data from a memory device coupled to the apparatus, cause a processing unit of at least one computing device of the plurality of computing devices to perform an operation on the block of data in which at least some of the data is ordered, reordered, removed, or discarded, and cause, after some of the data is ordered, reordered, removed, or discarded, the block of data to be transferred to the interface coupled to the plurality of computing devices.

Abstract: Systems, apparatuses, and methods related to arithmetic operations in memory are described. The arithmetic operations may be performed using bit strings and within a memory array without transferring the bit strings to circuitry external to the memory array. For instance, sensing circuitry that can include a sense amplifier and a compute component can be coupled to a memory array. A controller can be coupled to the sensing circuitry and can be configured to cause one or more bit strings to be transferred from the memory array to the sensing circuitry. In addition to the arithmetic operations, the sensing circuitry can also perform a logical operation using the one or more bit strings.

Abstract: Systems, apparatuses, and methods related to a neuron built with posits are described. An example system may include a memory device and the memory device may include a plurality of memory cells. The plurality of memory cells can store data including a bit string in an analog format. A neuromorphic operation can be performed on the data in the analog format. The example system may include an analog to digital converter coupled to the memory device. The analog to digital converter may convert the bit string in the analog format stored in at least one of the plurality of memory cells to a format that supports arithmetic operations to a particular level of precision.

Abstract: Systems, apparatuses, and methods related to bit string operations in memory are described. The bit string operations may be performed within a memory array without transferring the bit strings or intermediate results of the operations to circuitry external to the memory array. For instance, sensing circuitry that can include a sense amplifier and a compute component can be coupled to a memory array. A controller can be coupled to the sensing circuitry and can be configured to cause one or more bit strings that are formatted according to a universal number format or a posit format to be transferred from the memory array to the sensing circuitry. The sensing circuitry can perform an arithmetic operation, a logical operation, or both using the one or more bit strings.

Abstract: Systems, apparatuses, and methods related to acceleration circuitry are described. The acceleration circuitry may be deployed in a memory device and can include a memory resource and/or logic circuitry. The acceleration circuitry can perform operations on data to convert the data between one or more numeric formats, such as floating-point and/or universal number (e.g., posit) formats. The acceleration circuitry can perform arithmetic and/or logical operations on the data after the data has been converted to a particular format. For instance, the memory resource can receive data comprising a bit string having a first format that provides a first level of precision. The logic circuitry can receive the data from the memory resource and convert the bit string to a second format that provides a second level of precision that is different from the first level of precision.