Abstract: Systems, apparatuses, and methods related to a neuron using posits are described. An example apparatus may include a memory array including a plurality of memory cells configured to store data. The data can include a plurality of bit strings. The example apparatus may include a neuron component coupled to the memory array. The neuron component can include neuron circuitry configured to perform neuromorphic operations on at least one of the plurality of bit strings.

Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example method can include receiving, at a processing unit that is coupled between a host device and a non-volatile memory device, signaling indicative of a plurality of operations to be performed on data written to or read from the non-volatile memory device. The method can further include performing, at the processing unit, at least one operation of the plurality of operations in response to the signaling. The method can further include accessing a portion of a memory array in the non-volatile memory device. The method can further include transmitting additional signaling indicative of a command to perform one or more additional operations of the plurality of operations on the data written to or read from the non-volatile memory device.

Abstract: A method related to posit tensor processing can include receiving, by a plurality of multiply-accumulator (MAC) units coupled to one another, a plurality of universal number (unum) or posit bit strings organized in a matrix and to be used as operands in a plurality of respective recursive operations performed using the plurality of MAC units and performing, using the MAC units, the plurality of respective recursive operations. Iterations of the respective recursive operations are performed using at least one bit string that is a same bit string as was used in a preceding iteration of the respective recursive operations. The method can further include prior to receiving the plurality of unum or posit bit strings, performing an operation to organize the plurality of unum or posit bit strings to achieve a threshold bandwidth ratio, a threshold latency, or both during performance of the plurality of respective recursive operations.

Abstract: Systems, apparatuses, and methods related to arithmetic operations in memory are described. The arithmetic operations may be performed using bit strings and within a memory array without transferring the bit strings to circuitry external to the memory array. For instance, sensing circuitry that can include a sense amplifier and a compute component can be coupled to a memory array. A controller can be coupled to the sensing circuitry and can be configured to cause one or more bit strings to be transferred from the memory array to the sensing circuitry. In addition to the arithmetic operations, the sensing circuitry can also perform a logical operation using the one or more bit strings.

Abstract: Systems, apparatuses, and methods related to acceleration circuitry are described. The acceleration circuitry may be deployed in a memory device and can include a memory resource and/or logic circuitry. The acceleration circuitry can perform operations on data to convert the data between one or more numeric formats, such as floating-point and/or universal number (e.g., posit) formats. The acceleration circuitry can perform arithmetic and/or logical operations on the data after the data has been converted to a particular format. For instance, the memory resource can receive data comprising a bit string having a first format that provides a first level of precision. The logic circuitry can receive the data from the memory resource and convert the bit string to a second format that provides a second level of precision that is different from the first level of precision.

Abstract: Systems, apparatuses, and methods related to bit string compression are described. A method for bit string compression can include determining that a particular operation is to be performed using a bit string formatted according to a universal number format or a posit format to alter a bit width associated with the bit string from a first bit width to a second bit width and performing a compression operation on a bit string formatted according to a universal number format or a posit format to alter a bit width associated with the bit string from a first bit width to a second bit width. The method can further include writing the bit string having the second bit width to a first register, performing an arithmetic operation or a logical operation, or both using the bit string having the second bit string width, and monitoring a quantity of bits of a result of the operation.

Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example method includes receiving a request to access data via an input/output (I/O) device, determining whether the data is stored in a non-persistent memory device or a persistent memory device, and redirecting the request to access the data to logic circuitry in response to determining that the data is stored in the persistent memory device.

Abstract: Systems, apparatuses, and methods related to arithmetic operations in memory are described. The arithmetic operations may be performed using bit strings and within a memory array without transferring the bit strings to circuitry external to the memory array. For instance, sensing circuitry that can include a sense amplifier and a compute component can be coupled to a memory array. A controller can be coupled to the sensing circuitry and can be configured to cause one or more bit strings to be transferred from the memory array to the sensing circuitry. In addition to the arithmetic operations, the sensing circuitry can also perform a logical operation using the one or more bit strings.

Abstract: Systems, apparatuses, and methods related to hierarchical memory are described herein. A hierarchical memory apparatus can be part of a memory system that can leverage persistent memory to store data that is generally stored in a non-persistent memory. An example apparatus includes logic circuitry configured to receive a command indicating that an access to a base address register coupled to the logic circuitry has occurred. The command can be indicative of a data access involving a persistent memory device and/or a non-persistent memory device. The logic circuitry can determine that the access command corresponds to an operation to divert data from the non-persistent memory device to the persistent memory device, generate an interrupt signal, and cause the interrupt signal to be asserted on a host coupleable to the logic circuitry as part of the operation to divert data from the non-persistent memory device to the persistent memory device.

Abstract: Systems, apparatuses, and methods related to a selectively operable memory device are described. An example method corresponding to a selectively operable memory device can include receiving, by a resistance variable memory device, a command to operate the resistance variable memory device in a first mode or a second mode and operating the resistance variable memory device in the first mode or the second mode based, at least in part, on the received command to perform, in the first mode, a read operation or a write operation, or both, or, in the second mode, a compute operation. The method can further include performing, using a processing unit resident on the resistance variable memory device, the compute operation, the testing operation, or both based, at least in part, on a determination that the resistance variable memory device is operating in the second mode.

Abstract: Systems, apparatuses, and methods related to an extended memory neuromorphic component for performing operations in memory are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit and a memory array. The example apparatus can further include a communication subsystem coupled to the at least one of the plurality of computing devices and to a neuromorphic component. At least one of the plurality of computing devices can receive a request from a host to perform an operation, receive an indication of data to be access in a memory device to perform the operation, and send an indication to the neuromorphic component to monitor the data to be accessed. The neuromorphic component can intercept data and determine that a portion of the data should be flagged.

Abstract: Systems, apparatuses, and methods related to a neuron built with posits are described. An example system may include a memory device and the memory device may include a plurality of memory cells. The plurality of memory cells can store data including a bit string in an analog format. A neuromorphic operation can be performed on the data in the analog format. The example system may include an analog to digital converter coupled to the memory device. The analog to digital converter may convert the bit string in the analog format stored in at least one of the plurality of memory cells to a format that supports arithmetic operations to a particular level of precision.

Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit configured to perform an operation on a block of data, and a memory array configured as a cache for each respective processing unit. The example apparatus can further include a first communication subsystem coupled to a host and to each of the plurality of communication subsystems. The example apparatus can further include a plurality of second communication subsystems coupled to each of the plurality of computing devices. Each of the plurality of computing devices can be configured to receive a request from the host, send a command to execute at least a portion of the operation, and receive a result of performing the operation from the at least one hardware accelerator.

Abstract: Systems, apparatuses, and methods related to extended memory microcode components for performing extended memory operations are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit and a memory array. The example apparatus can include a plurality of microcode components coupled to each of the plurality of computing devices and each comprise a set of microcode instructions. The example apparatus can further include a communication subsystem coupled to a host and to each of the plurality of computing devices. Each of the plurality of computing devices can be configured to receive a request from the host, retrieve at least one of the set of microcode instructions, transfer a command and the at least one of the set of microcode instructions, and receive a result of performing the operation.

Abstract: Methods, Systems, and Apparatuses related to application-based data type selection are described. A processing device perform operations to monitor performance characteristics associated with various applications executed by a host computing device to determine that a threshold performance level has been reached or exceeded. Operations to convert a data type utilized by the various applications from a first format that supports arithmetic operations to a first level of precision to a second format that supports arithmetic operations to a second level of precision can be performed based, at least in part, on the determination.

Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example method includes initiating a read request associated with an address from an input/output device, redirecting the read request to a hierarchical memory component, generating, by the hierarchical memory component, an interrupt message to send to a hypervisor, gathering, at the hypervisor, address register access information from the hierarchical memory component, and determining a physical location of data associated with the read request.

Abstract: Methods, Systems, and apparatuses related to performing bit string accumulation within a compute or memory device are described. A logic circuit with processing capability and a register within or near memory, for example, can perform multiple iterations of a recursive operation using several bit strings. Results of the various iterations may be written to the register, and subsequent iterations of the recursive operation using the bit strings may be performed. Results of the iterations of recursive operations may be accumulated within the register. Accumulated results may be written as data to another register or to memory that is external to or separate from the logic circuit.

Abstract: Systems, apparatuses, and methods related to dynamic precision bit string accumulation are described. Dynamic bit string accumulation can be performed using an edge computing device. In an example method, dynamic precision bit string accumulation can include performing an iteration of a recursive operation using a first bit string and a second bit string and determining that a result of the iteration of the recursive operation contains a quantity of bits in a particular bit sub-set of the result that is greater than a threshold quantity of bits associated with the particular bit sub-set. The method can further include writing a result of the iteration of the recursive operation to a first register and writing at least a portion of the bits associated with the particular bit sub-set of the result to a second register.

Abstract: Methods, systems, and apparatuses related to training neural networks are described. For example, data management and training of one or more neural networks may be accomplished within a memory device, such as a dynamic random-access memory (DRAM) device. Neural networks may thus be trained in the absence of specialized circuitry and/or in the absence of vast computing resources. One or more neural networks may be written or stored within memory banks of a memory device and operations may be performed within or adjacent to those memory banks to train different neural networks that are located in different banks of the memory device. This data management and training may occur within a memory system without involving a host device, processor, or accelerator that is external to the memory system. A trained network may then be read from the memory system and used for inference or other operations on an external device.

Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices coupled to one another. Each of the plurality of computing devices can include a processing unit configured to perform an operation on a block of data in response to receipt of the block of data. Each of the plurality of computing devices can further include a memory array configured as a cache for the processing unit. The example apparatus can further include a first plurality of communication subsystems coupled to the plurality of computing devices and to a second plurality of communication subsystems. The first and second plurality of communication subsystems are configured to request and/or transfer the block of data.