Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. In an example apparatus, an input/output (I/O) device can receive signaling that includes a command to write to or read data from an address corresponding to a non-persistent memory device, and can determine where to redirect the request. For example, the I/O device can determine to write or read data to and/or from the non-persistent memory device or the persistent memory device based at least in part on one or more characteristics of the data.

Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. An example method includes receiving a request to store data in a persistent memory device and a non-persistent memory device via an input/output (I/O) device; redirecting the request to store the data to logic circuitry in response to determining that the request corresponds to performance of a hierarchical memory operation; storing in a base address register associated with the logic circuitry, logical address information corresponding to the data responsive to receipt of the redirected request; asserting, by the logic circuitry, an interrupt signal on a hypervisor, the interrupt signal indicative of initiation of an operation to be performed by the hypervisor to control access to the data by the logic circuitry; and writing, based at least in part, on receipt of the redirected request, the data to the persistent memory device and the non-persistent memory device substantially concurrently.

Abstract: Apparatuses, systems, and methods corresponding to hierarchical memory systems are described. Logic circuitry can be resident on a persistent memory device, thereby reducing latencies associated with transferring data between the logic circuitry and the persistent memory device. Logic circuitry on a persistent memory device may include an address register configured to store logical addresses corresponding to stored data. The logic circuitry may receive a redirected request (e.g., prior to redirection, directed to a non-persistent memory device) to retrieve a portion of the data stored in the persistent memory device, determine, in response to receipt of the request to retrieve the portion of the stored data, a physical address corresponding to the portion of the data based on the logical address stored in the address register, and cause the data to be retrieved from the persistent memory device.

Abstract: Systems, apparatuses, and methods related to hierarchical memory are described herein. Hierarchical memory can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. Hierarchical memory may include an address register configured to store addresses corresponding to data stored in a persistent memory device, and circuitry configured to receive, from memory management circuitry, a request to access a portion of the data stored in the persistent memory device, determine an address corresponding to the portion of the data using the register, generate another request to access the portion of the data, and send the other request to the persistent memory device to access the portion of the data.

Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example method includes receiving an interrupt message by a hypervisor, the interrupt message generated by a hierarchical memory component responsive to receiving a read request initiated by an input/output (I/O) device, gathering, by the hypervisor, address register access information from the hierarchical memory component, and determining, by the hypervisor, a physical location of data associated with the read request.

Abstract: Systems, apparatuses, and methods related to hierarchical memory are described herein. A hierarchical memory apparatus can be part of a memory system that can leverage persistent memory to store data that is generally stored in a non-persistent memory. An example apparatus includes logic circuitry configured to receive a command indicating that an access to a base address register coupled to the logic circuitry has occurred. The command can be indicative of a data access involving a persistent memory device and/or a non-persistent memory device. The logic circuitry can determine that the access command corresponds to an operation to divert data from the non-persistent memory device to the persistent memory device, generate an interrupt signal, and cause the interrupt signal to be asserted on a host coupleable to the logic circuitry as part of the operation to divert data from the non-persistent memory device to the persistent memory device.

Abstract: Systems, apparatuses, and methods related to hierarchical memory are described. A hierarchical memory system that can leverage persistent memory to store data that is generally stored in a non-persistent memory. Logic circuitry can be configured to determine that a request to access a persistent memory device corresponds to an operation to divert data from the non-persistent memory device to the persistent memory device, generate an interrupt signal, and cause the interrupt signal to be asserted on a host coupleable to the logic circuitry as part of the operation to divert data from the non-persistent memory device to the persistent memory device. Access data and control messages can be transferred between or within a memory device, including to or from a multiplexer and/or a state machine. A state machine can include logic circuitry configured to transfer interrupt request messages to and receive interrupt request messages.

Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. An example method includes receiving a request to store data in a persistent memory device and a non-persistent memory device via an input/output (I/O) device; redirecting the request to store the data to logic circuitry in response to determining that the request corresponds to performance of a hierarchical memory operation; storing in a base address register associated with the logic circuitry, logical address information corresponding to the data responsive to receipt of the redirected request; asserting, by the logic circuitry, an interrupt signal on a hypervisor, the interrupt signal indicative of initiation of an operation to be performed by the hypervisor to control access to the data by the logic circuitry; and writing, based at least in part, on receipt of the redirected request, the data to the persistent memory device and the non-persistent memory device substantially concurrently.

Abstract: Systems, apparatuses, and methods related to bit string operations in memory are described. The bit string operations may be performed within a memory array without transferring the bit strings or intermediate results of the operations to circuitry external to the memory array. For instance, sensing circuitry that can include a sense amplifier and a compute component can be coupled to a memory array. A controller can be coupled to the sensing circuitry and can be configured to cause one or more bit strings that are formatted according to a universal number format or a posit format to be transferred from the memory array to the sensing circuitry. The sensing circuitry can perform an arithmetic operation, a logical operation, or both using the one or more bit strings.

Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices coupled to one another. Each of the plurality of computing devices can include a processing unit configured to perform an operation on a block of data in response to receipt of the block of data. Each of the plurality of computing devices can further include a memory array configured as a cache for the processing unit. The example apparatus can further include a first plurality of communication subsystems coupled to the plurality of computing devices and to a second plurality of communication subsystems. The first and second plurality of communication subsystems are configured to request and/or transfer the block of data.

Abstract: Systems, apparatuses, and methods related to bit string conversion are described. A memory resource and/or logic circuitry may be used in performance of bit string conversion operations. The logic circuitry can perform operations on bit strings, such as universal number and/or posit bit strings, to alter a level of precision (e.g., a dynamic range, resolution, etc.) of the bit strings. For instance, the memory resource can receive data comprising a bit string having a first quantity of bits that correspond to a first level of precision. The logic circuitry can determine that the bit string having the first quantity of bits has a particular data pattern and alter the first quantity of bits to a second quantity of bits that correspond to a second level of precision based, at least in part, on the determination that the bit string has the particular data pattern.

Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example method can include receiving, at a processing unit that is coupled between a host device and a non-volatile memory device, signaling indicative of a plurality of operations to be performed on data written to or read from the non-volatile memory device. The method can further include performing, at the processing unit, at least one operation of the plurality of operations in response to the signaling. The method can further include accessing a portion of a memory array in the non-volatile memory device. The method can further include transmitting additional signaling indicative of a command to perform one or more additional operations of the plurality of operations on the data written to or read from the non-volatile memory device.

Abstract: Systems, apparatuses, and methods related to bit string compression are described. A method for bit string compression can include determining that a particular operation is to be performed using a bit string formatted according to a universal number format or a posit format to alter a bit width associated with the bit string from a first bit width to a second bit width and performing a compression operation on a bit string formatted according to a universal number format or a posit format to alter a bit width associated with the bit string from a first bit width to a second bit width. The method can further include writing the bit string having the second bit width to a first register, performing an arithmetic operation or a logical operation, or both using the bit string having the second bit string width, and monitoring a quantity of bits of a result of the operation.

Abstract: Systems, apparatuses, and methods related to bit string operations using a computing tile are described. An example apparatus includes computing device (or “tile”) that includes a processing unit and a memory resource configured as a cache for the processing unit. A data structure can be coupled to the computing device. The data structure can be configured to receive a bit string that represents a result of an arithmetic operation, a logical operation, or both and store the bit string that represents the result of the arithmetic operation, the logical operation, or both. The bit string can be formatted in a format different than a floating-point format.

Abstract: Systems, apparatuses, and methods related to bit string accumulation in memory array periphery are described. Control circuitry (e.g., a processing device) may be utilized to control performance of operations using bit strings within a memory device. Results of the operations may be accumulated in circuitry peripheral to a memory array of the memory device. For instance, a method for bit string accumulation in memory array periphery can include performing a first operation using a first bit string and a second bit string and retrieving a third bit string from a memory array or a storage location located in the periphery of the memory array. The method can further include performing a second operation using the result of the first operation and the third bit string and storing the result of the second operation in the storage location located in the periphery of the memory array.

Abstract: Systems, apparatuses, and methods related to an extended memory communication subsystem for performing extended memory operations are described. An example apparatus can include a plurality of computing devices coupled to one another. Each of the plurality of computing devices can include a processing unit configured to perform an operation on a block of data in response to receipt of the block of data. Each of the plurality of computing devices can further include a memory array configured as a cache for the processing unit. The example apparatus can further include a first communication subsystem within the apparatus and coupled to the plurality of computing devices and to a controller, wherein the first communication subsystem is configured to request the block of data. The example apparatus can further include a second communication subsystem within the apparatus and coupled to the plurality of computing devices and to the controller.

Abstract: Bit string accumulation in a memory array periphery is described. Control circuitry (e.g., a processing device) may be utilized to control performance of operations using bit strings within a memory device. Results of the operations may be accumulated in circuitry peripheral to a memory array of the memory device. For instance, a plurality of sense amplifiers may be coupled to a memory array and a processing device. A quantity of sense amplifiers among the plurality of sense amplifiers can be the same as a quantity of rows or columns of the array. The processing device may be configured to cause performance of a recursive operation using one or more bit strings that are formatted according to a Type III universal number format or a posit format. The processing device may further be configured to cause resultant bit strings representing results of iterations of the recursive operation to be accumulated in the plurality of sense amplifiers.

Abstract: Systems, apparatuses, and methods related to bit string accumulation in memory array periphery are described. Control circuitry (e.g., a processing device) may be utilized to control performance of operations using bit strings within a memory device. Results of the operations may be accumulated in circuitry peripheral to a memory array of the memory device. For instance, a method for bit string accumulation in memory array periphery can include retrieving a bit string stored in a data structure of a memory array. The bit string can represent a result of performance of an arithmetic operation or a logical operation. The method can further include storing the bit string in a plurality of sense amplifiers located in a periphery of the memory array and using the bit string as an operand in performance of at least a portion of a recursive operation.

Abstract: Systems, apparatuses, and methods related to bit string conversion are described. A memory resource and/or logic circuitry may be used in performance of bit string conversion operations. The logic circuitry can perform operations on bit strings, such as universal number and/or posit bit strings, to alter a level of precision (e.g., a dynamic range, resolution, etc.) of the bit strings. For instance, the memory resource can receive data comprising a bit string having a first quantity of bits that correspond to a first level of precision. The logic circuitry can determine that the bit string having the first quantity of bits has a particular data pattern and alter the first quantity of bits to a second quantity of bits that correspond to a second level of precision based, at least in part, on the determination that the bit string has the particular data pattern.

Abstract: Systems, apparatuses, and methods related to bit string operations using a computing tile are described. An example apparatus includes a computing device (or “tile”) including a processing unit and a memory resource configured as a cache for the processing unit. The computing device can include circuitry to receive a command to initiate an operation to convert data comprising a bit string having a first format that supports arithmetic operations to a first level of precision to a bit string having a second format that supports arithmetic operations to a second level of precision. The computing device can receive, by the memory resource, the bit string based, at least in part, on receipt of the command and, responsive to receipt of the data, perform the operation on the bit string to convert the data from the first format to the second format.