Patents by Inventor Vijayeshwar D. Khanna
Vijayeshwar D. Khanna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150041524Abstract: A vacuum carrier can be employed to provide a partial vacuum on a back side surface of a substrate thereby holding the substrate flat against a rigid surface of the carrier throughout the duration of a bonding process. The magnitude of vacuum can be optimized to limit the warping of the substrate during and after bonding with another substrate, and to limit the mechanical stress induced in the solder balls during cooling. The vacuum carrier can include a base plate, a seal plate with at least one opening configured to accommodate at least one substrate, and vacuum seal elements configured to create a vacuum environment that pushes the substrate against the base plate when the vacuum carrier is under vacuum. The configuration of the vacuum carrier is chosen to avoid distortion of the substrate due to the vacuum seal elements, while allowing adjustment of the magnitude of the partial vacuum.Type: ApplicationFiled: August 6, 2013Publication date: February 12, 2015Applicant: International Business Machines CorporationInventors: Vijayeshwar D. Khanna, Sri M. Sri-Jayantha
-
Publication number: 20150024549Abstract: The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail.Type: ApplicationFiled: July 22, 2013Publication date: January 22, 2015Applicant: International Business Machines CorporationInventors: Evan G. Colgan, Steven A. Cordes, Daniel C. Edelstein, Vijayeshwar D. Khanna, Kenneth Latzko, Qinghuang Lin, Peter J. Sorce, Sri M. Sri-Jayantha, Robert L. Wisnieff, Roy R. Yu
-
Publication number: 20150000868Abstract: A structure and method of mounting a heat sink having a body and mounting points configured so as to connect to a mounting medium, at least one of the mounting points being configured to allow movement in a thermally-induced expansion direction.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Applicant: International Business Machines CorporationInventors: Sri M Sri-Jayantha, Gerard McVicker, JR., Vijayeshwar D Khanna, JR.
-
Publication number: 20150000097Abstract: A method of mounting a heat sink includes providing a heat sink having a plurality of mounting points, and attaching a plurality of mounting members to the heat sink at the plurality of mounting points, respectively, at least one of a combination of a mounting point of the mounting points and a mounting member of the mounting members being configured so as to have a stiffness in a thermally-induced expansion direction of the heat sink at the respective mounting point which is less than a stiffness in an other direction at the respective mounting point.Type: ApplicationFiled: October 3, 2013Publication date: January 1, 2015Applicant: International Business Machines CorporationInventors: Sri M. Sri-Jayantha, Gerard McVicker, Vijayeshwar D. Khanna
-
Publication number: 20140359995Abstract: A clamping apparatus applies a force to a workpeice during processing. The clamping apparatus includes a base defining a work area configured to receive a joined structure having multiple elements. The base defines a recess in the work area. An adjustable mechanism is configured to releasably couple to the base and apply a adjustable downward force to the joined structure to bend the joined structure downwardly into the recess during a process. A resilient plunger is part of the adjustable mechanism. The resilient plunger extends downwardly from a top plate of the adjustable mechanism, and the resilient plunger is configured to contact a top of a first element of the joined structure to apply the downward force.Type: ApplicationFiled: June 5, 2013Publication date: December 11, 2014Inventors: Edmund Blackshear, Vijayeshwar D. Khanna, Oswald J. Mantilla
-
Publication number: 20140151849Abstract: An electronic module includes a substrate including at least one structure that reduces stress flow through the substrate, wherein the structure includes at least one trench in a surface of the substrate, and a plurality of capacitor legs disposed on an upper surface of the substrate.Type: ApplicationFiled: January 17, 2014Publication date: June 5, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Questad, Vijayeshwar D. Khanna, Jennifer V. Muncy, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit
-
Patent number: 8685833Abstract: A method is provided for bonding a semiconductor chip to a packaging substrate while minimizing the variation in the solder ball heights and controlling the stress in the solder balls and the stress in the packaging substrate. During the solder reflow, the warp of the packaging substrate, including the absolute warp, thermal warp, and substrate to substrate variations of the warp, is constrained at a minimal level by providing a clamping constraint to the packaging substrate. During cool down of the solder balls, the stresses and strains of the solder joints are maintained at levels that do not cause tear of the solder joints or breakage of the packaging substrate by removing the clamping constraint. Thus, the bonding process provides both uniform solder height with minimized solder non-wets and stress minimization of the solder balls and the packaging substrate.Type: GrantFiled: April 2, 2012Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Vijayeshwar D. Khanna, Sri M. Sri-Jayantha
-
Patent number: 8624152Abstract: Methods for the fabrication of negative coefficient thermal expansion engineered elements, and particularly, wherein such elements provide for fillers possessing a low or even potentially zero coefficient thermal expansion and which are employable as fillers for polymers possessing high coefficients of thermal expansion. Further, disclosed are novel structures, which are obtained by the inventive methods.Type: GrantFiled: January 24, 2012Date of Patent: January 7, 2014Assignee: International Business Machines CorporationInventors: Gareth G. Hougham, Vijayeshwar D. Khanna, Xiao Hu Liu, Gerard McVicker
-
Publication number: 20130260534Abstract: A method is provided for bonding a semiconductor chip to a packaging substrate while minimizing the variation in the solder ball heights and controlling the stress in the solder balls and the stress in the packaging substrate. During the solder reflow, the warp of the packaging substrate, including the absolute warp, thermal warp, and substrate to substrate variations of the warp, is constrained at a minimal level by providing a clamping constraint to the packaging substrate. During cool down of the solder balls, the stresses and strains of the solder joints are maintained at levels that do not cause tear of the solder joints or breakage of the packaging substrate by removing the clamping constraint. Thus, the bonding process provides both uniform solder height with minimized solder non-wets and stress minimization of the solder balls and the packaging substrate.Type: ApplicationFiled: April 2, 2012Publication date: October 3, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vijayeshwar D. Khanna, Sri M. Sri-Jayantha
-
Publication number: 20120309187Abstract: Thermal deformation of a substrate and the substrate's warp at room temperature are used to determine the expected profile of the substrate at reflow. A contact surface profile of a coining pressure plate is selected based on the expected substrate profile. A solder surface is shaped on the substrate or a die to be joined to the substrate by the coining pressure plate, thereby facilitating the chip-joining process.Type: ApplicationFiled: July 29, 2011Publication date: December 6, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sri M. Sri-Jayantha, Vijayeshwar D. Khanna
-
Patent number: 8322980Abstract: A cooling system includes a moving rotor system which in turn includes: a rotating disk on which a plurality of heat conducting structures are distributed, the heat conducting structures including an inner arrangement of spiral blades; an air flow generating fan element; and an outer arrangement of heat transfer pins distributed along a perimeter of the rotating disk, the heat transfer pins having a high aspect ratio that maximizes a surface area to footprint area; wherein the spiral blades generate a mass fluid flow of ambient fluid toward the heat transfer pins such that the heat transfer pins are persistently cooled.Type: GrantFiled: January 28, 2011Date of Patent: December 4, 2012Assignee: International Business Machines CorporationInventors: Vijayeshwar D. Khanna, Gerard McVicker, Sri M. Sri-Jayantha
-
Publication number: 20120121906Abstract: Methods for the fabrication of negative coefficient thermal expansion engineered elements, and particularly, wherein such elements provide for fillers possessing a low or even potentially zero coefficient thermal expansion and which are employable as fillers for polymers possessing high coefficients of thermal expansion. Further, disclosed are novel structures, which are obtained by the inventive methods.Type: ApplicationFiled: January 24, 2012Publication date: May 17, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gareth G. Hougham, Vijayeshwar D. Khanna, Xiao Hu Liu, Gerard McVicker
-
Patent number: 8138448Abstract: Methods for the fabrication of negative coefficient thermal expansion engineered elements, and particularly, wherein such elements provide for fillers possessing a low or even potentially zero coefficient thermal expansion and which are employable as fillers for polymers possessing high coefficients of thermal expansion. Further, disclosed are novel structures, which are obtained by the inventive methods.Type: GrantFiled: December 31, 2007Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Gareth G. Hougham, Vijayeshwar D. Khanna, Xiao Hu Liu, Gerard McVicker
-
Patent number: 8054630Abstract: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.Type: GrantFiled: February 13, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: David Questad, Vijayeshwar D. Khanna, Jennifer V. Muney, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit
-
Publication number: 20110123318Abstract: A cooling system includes a moving rotor system which in turn includes: a rotating disk on which a plurality of heat conducting structures are distributed, the heat conducting structures including an inner arrangement of spiral blades; an air flow generating fan element; and an outer arrangement of heat transfer pins distributed along a perimeter of the rotating disk, the heat transfer pins having a high aspect ratio that maximizes a surface area to footprint area; wherein the spiral blades generate a mass fluid flow of ambient fluid toward the heat transfer pins such that the heat transfer pins are persistently cooled.Type: ApplicationFiled: January 28, 2011Publication date: May 26, 2011Applicant: International Business Machines CorporationInventors: Vijayeshwar D. Khanna, Gerard McVicker, Sri M. Sri-Jayantha
-
Patent number: 7901998Abstract: A pattern matched pair of a front metal interconnect layer and a back metal interconnect layer having matched thermal expansion coefficients are provided for a reduced warp packaging substrate. Metal interconnect layers containing a high density of wiring and complex patterns are first developed so that interconnect structures for signal transmission are optimized for electrical performance. Metal interconnect layers containing a low density wiring and relatively simple patterns are then modified to match the pattern of a mirror image metal interconnect layer located on the opposite side of the core and the same number of metal interconnect layer away from the core. During this pattern-matching process, the contiguity of electrical connection in the metal layers with a low density wiring may become disrupted. The disruption is healed by an additional design step in which the contiguity of the electrical connection in the low density is reestablished.Type: GrantFiled: May 7, 2010Date of Patent: March 8, 2011Assignee: International Business Machines CorporationInventors: Sri M. Sri-Jayantha, Hien P. Dang, Vijayeshwar D. Khanna, Arun Sharma
-
Patent number: 7896611Abstract: A cooling system includes a moving rotor system which in turn includes: a disk on which a plurality of heat conducting structures are distributed, the heat conducting structures having a cross section optimized for maximum surface area to footprint area; the heat conducting structures having a shape to optimize the heat transfer coefficient between the structures moving through the ambient fluid; and a mechanism for generating a mass fluid flow over the conducting structures so that the heat conducting structures are persistently cooled.Type: GrantFiled: January 3, 2007Date of Patent: March 1, 2011Assignee: International Business Machines CorporationInventors: Vijayeshwar D. Khanna, Gerard McVicker, Sri M. Sri-Jayantha
-
Patent number: 7855430Abstract: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.Type: GrantFiled: April 8, 2008Date of Patent: December 21, 2010Assignee: International Business Machines CorporationInventors: David Questad, Vijayeshwar D. Khanna, Jennifer V. Muncy, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit
-
Patent number: 7819027Abstract: A tensile strength testing structure for controlled collapse chip connections (C4) disposed above a substrate includes: a fixture base configured for positioning substrates with C4; a top fixture plate with through hole channels; test pins for insertion through the through hole channels; wherein dimensional tolerances of the substrates are accounted for with openings on at least two sides of the fixture base for positioning the substrates, and during alignment of the top fixture plate through hole channels with the C4 prior to securing the top fixture plate to the fixture base; wherein the test pins are strain hardened metal wires; wherein lower ends of the test pins are joined to the C4 during a solder reflow process; and wherein distal ends of the test pins are pulled in a direction perpendicular to the testing structure to determine the tensile strength of the C4.Type: GrantFiled: June 22, 2007Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: Virendra R. Jadhav, Vijayeshwar D. Khanna, David C. Long, David L. Questad
-
Publication number: 20100218364Abstract: A pattern matched pair of a front metal interconnect layer and a back metal interconnect layer having matched thermal expansion coefficients are provided for a reduced warp packaging substrate. Metal interconnect layers containing a high density of wiring and complex patterns are first developed so that interconnect structures for signal transmission are optimized for electrical performance. Metal interconnect layers containing a low density wiring and relatively simple patterns are then modified to match the pattern of a mirror image metal interconnect layer located on the opposite side of the core and the same number of metal interconnect layer away from the core. During this pattern-matching process, the contiguity of electrical connection in the metal layers with a low density wiring may become disrupted. The disruption is healed by an additional design step in which the contiguity of the electrical connection in the low density is reestablished.Type: ApplicationFiled: May 7, 2010Publication date: September 2, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sri M. Sri-Jayantha, Hien P. Dang, Vijayeshwar D. Khanna, Arun Sharma