Patents by Inventor Violante Moschiano

Violante Moschiano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Charge loss compensation methods and apparatus
    Patent number: 8767476
    Abstract: Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: July 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Daniel Elmhurst, Paul Ruby
  • MEMORY CELL SENSING USING A BOOST VOLTAGE
    Publication number: 20140177342
    Abstract: The present disclosure includes devices, methods, and systems including memory cell sensing using a boost voltage. One or more embodiments include pre-charging and/or floating a data line associated with a selected memory cell, boosting the pre-charged and/or floating data line, and determining a state of the selected memory cell based on a sensed discharge of the data line after boosting the data line.
    Type: Application
    Filed: December 18, 2013
    Publication date: June 26, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Violante Moschiano, Domenico Di Cicco, Andrea D'Alessandro
  • Determining soft data for combinations of memory cells
    Patent number: 8737139
    Abstract: The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells including a first and a second memory cell each programmable to one of a number of program states, wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states, and a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program states of the first and second memory cells.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: May 27, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Tommaso Vali, Mark A. Hawes
  • ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING
    Publication number: 20140133224
    Abstract: Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
    Type: Application
    Filed: January 23, 2014
    Publication date: May 15, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Tommaso Vali, Giovanni Santin, Michele Incarnati, Violante Moschiano
  • METHODS OF PROGRAMMING MEMORY DEVICES
    Publication number: 20140112068
    Abstract: Methods of programming memory devices include biasing each data line of a plurality of data lines to a program inhibit voltage; discharging a first portion of data lines of the plurality of data lines, wherein the first portion of data lines of the plurality of data lines are coupled to memory cells selected for programming; and applying a plurality of programming pulses to the memory cells selected for programming while biasing a remaining portion of data lines of the plurality of data lines to the program inhibit voltage.
    Type: Application
    Filed: December 30, 2013
    Publication date: April 24, 2014
    Applicant: Micro Technology, Inc.
    Inventors: Akira Goda, Andrew Bicksler, Violante Moschiano, Giuseppina Puzzilli
  • Non-volatile memory programming
    Patent number: 8705277
    Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying different voltages to data lines associated with different memory cells based on threshold voltages of the memory cells in an erased state. Other embodiments including additional memory devices and methods are described.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Giovanni Santin
  • Memories and methods of programming memories
    Patent number: 8681562
    Abstract: Apparatus and methods for adjusting programming for upper pages of memories are disclosed. In at least one embodiment, a threshold voltage distribution upper limit is determined after a single programming pulse for lower page programming, and upper page programming start voltages are adjusted based on the determined upper limit of the threshold voltage distribution.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Pranav Kalavade, Akira Goda, Tommaso Vali, Violante Moschiano
  • Word line voltage boost system and method for non-volatile memory devices and memory devices and processor-based system using same
    Patent number: 8681559
    Abstract: The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line by increasing the voltages of the adjacent word lines after a programming voltage has been applied to a string driver transistor for the selected word line and after a string driver voltage has been applied to the gates of all of the string driver transistors in an array.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Giovanni Santin, Ercole di Iorio
  • METHOD FOR KINK COMPENSATION IN A MEMORY
    Publication number: 20140043912
    Abstract: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
    Type: Application
    Filed: October 3, 2013
    Publication date: February 13, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Violante Moschiano, Frankie Roohparvar, Giovanni Santin, Vishal Sarin, Allahyar Vahidimowlavi, Tommaso Vali
  • Architecture and method for memory programming
    Patent number: 8638624
    Abstract: Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: January 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Tommaso Vali, Giovanni Santin, Michele Incarnati, Violante Moschiano
  • MULTIPLE STEP PROGRAMMING IN A MEMORY DEVICE
    Publication number: 20140016409
    Abstract: A method for multiple step programming programs data to an even page of memory cells. The even page of memory cells is read into a page buffer and the uncertain data is removed. An odd page of memory cells is programmed and the data from the even page data from the page buffer is reprogrammed to the even page of memory cells without the uncertain data.
    Type: Application
    Filed: July 13, 2012
    Publication date: January 16, 2014
    Inventors: Violante Moschiano, Mason Jones
  • Memory cell sensing using a boost voltage
    Patent number: 8630125
    Abstract: The present disclosure includes devices, methods, and systems including memory cell sensing using a boost voltage. One or more embodiments include pre-charging and/or floating a data line associated with a selected memory cell, boosting the pre-charged and/or floating data line, and determining a state of the selected memory cell based on a sensed discharge of the data line after boosting the data line.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: January 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Domenico Di Cicco, Andrea D'Alessandro
  • Data line management in a memory device
    Patent number: 8619474
    Abstract: Memory devices and methods are disclosed, such as devices configured to apply a first program inhibit bias to data lines during a first portion of a program operation and to apply a second program inhibit bias to data lines during a second portion of the program operation. The second program inhibit bias is greater than the first program inhibit bias.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: December 31, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Andrew Bicksler, Violante Moschiano, Giuseppina Puzzilli
  • MEMORY ARRAYS AND METHODS OF OPERATING MEMORY
    Publication number: 20130343132
    Abstract: Apparatus and methods for determining pass/fail condition of memories are disclosed. In at least one embodiment, a set of common lines, one for each rank of page buffers corresponding to a page, determine the pass/fail status of all connected memory cells, and the pass/fail status results for each line can be combined to determine a pass/fail for the page of memory.
    Type: Application
    Filed: August 28, 2013
    Publication date: December 26, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Violante MOSCHIANO, Giovanni SANTIN
  • Sensing scheme in a memory device
    Patent number: 8593876
    Abstract: Methods of operating memory devices, generating reference currents in memory devices, and sensing data states of memory cells in a memory device are disclosed. One such method includes generating reference currents utilized in sense amplifier circuitry to manage leakage currents while performing a sense operation within a memory device. Another such method activates one of two serially coupled transistors along with activating and deactivating the second transistor serially coupled with the first transistor thereby regulating a current through both serially coupled transistors and establishing a particular reference current.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: November 26, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Giovanni Santin, Tommaso Vali
  • NON-VOLATILE MEMORY PROGRAMMING
    Publication number: 20130286743
    Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described.
    Type: Application
    Filed: June 24, 2013
    Publication date: October 31, 2013
    Inventors: Paul D. Ruby, Violante Moschiano, Giovanni Santin
  • DETERMINING SOFT DATA FOR COMBINATIONS OF MEMORY CELLS
    Publication number: 20130272071
    Abstract: The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells including a first and a second memory cell each programmable to one of a number of program states, wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states, and a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program states of the first and second memory cells.
    Type: Application
    Filed: April 11, 2012
    Publication date: October 17, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Violante Moschiano, Tommaso Vali, Mark A. Hawes
  • LEVEL COMPENSATION IN MULTILEVEL MEMORY
    Publication number: 20130265827
    Abstract: Some embodiments include apparatuses and methods having a compensation unit to provide a compensation value based at least in part on a threshold voltage value of a memory cell. At least one of such embodiments includes a controller to select a code during an operation of retrieving information from the memory cell to represent a value of information stored in the memory cell. Such a code can be associated with an address having an address value based at least in part on the compensation value. Additional apparatuses and methods are described.
    Type: Application
    Filed: July 31, 2012
    Publication date: October 10, 2013
    Inventors: Violante Moschiano, Walter Di Francesco
  • Method for kink compensation in a memory
    Patent number: 8553461
    Abstract: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: October 8, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Frankie Roohparvar, Giovanni Santin, Vishal Sarin, Allahyar Vahidimowlavi, Tommaso Vali
  • Memory arrays and methods of operating memory
    Patent number: 8526238
    Abstract: Apparatus and methods for determining pass/fail condition of memories are disclosed. In at least one embodiment, a set of common lines, one for each rank of page buffers corresponding to a page, determine the pass/fail status of all connected memory cells, and the pass/fail status results for each line can be combined to determine a pass/fail for the page of memory.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: September 3, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Giovanni Santin