Patents by Inventor Violante Moschiano

Violante Moschiano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Threshold voltage analysis
    Patent number: 9659639
    Abstract: Apparatuses and methods for threshold voltage analysis are described. One or more methods for threshold voltage analysis include storing expected state indicators corresponding to a group of memory cells, applying a first sensing voltage to a selected access line to which the group of memory cells is coupled, sensing whether at least one of the memory cells of the group conducts responsive to the first sensing voltage, determining whether a discharge indicator for the at least one of the memory cells has changed responsive to application of the first sensing voltage, and determining that the first sensing voltage is the threshold voltage for a particular program state of the at least one of the memory cells.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: May 23, 2017
    Assignee: Micron Technology, Inc.
    Inventors: William C. Filipiak, Violante Moschiano
  • Memory apparatus, systems, and methods
    Patent number: 9646683
    Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: May 9, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Tommaso Vali, Giovanni Naso, Vishal Sarin, William Henry Radke, Theodore T. Pekny
  • High performance memory controller
    Patent number: 9639420
    Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: May 2, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Walter Di Francesco, Luca De Santis, Giovanni Santin
  • Level compensation in multilevel memory
    Patent number: 9620236
    Abstract: Some embodiments include apparatuses and methods having a compensation unit to provide a compensation value based at least in part on a threshold voltage value of a memory cell. At least one of such embodiments includes a controller to select a code during an operation of retrieving information from the memory cell to represent a value of information stored in the memory cell. Such a code can be associated with an address having an address value based at least in part on the compensation value. Additional apparatuses and methods are described.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: April 11, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Walter Di Francesco
  • Pre-compensation of memory threshold voltage
    Patent number: 9589659
    Abstract: Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: March 7, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Tommaso Vali, Andrea D'Alessandro, Violante Moschiano, Mattia Cichocki, Michele Incarnati, Federica Paolini
  • Non-volatile memory programming
    Patent number: 9558831
    Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: January 31, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Paul D. Ruby, Violante Moschiano, Giovanni Santin
  • CONCURRENTLY READING FIRST AND SECOND PAGES OF MEMORY CELLS HAVING DIFFERENT PAGE ADDRESSES
    Publication number: 20170025181
    Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.
    Type: Application
    Filed: October 7, 2016
    Publication date: January 26, 2017
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
  • Determining soft data for combinations of memory cells
    Patent number: 9543000
    Abstract: The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells including a first and second memory cell each programmable to one of a number of program states, wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states, and a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program states of the first and second memory cells.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: January 10, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Tommaso Vali, Mark A. Hawes
  • DETERMINING SOFT DATA
    Publication number: 20170004878
    Abstract: The present disclosure includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. In a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell.
    Type: Application
    Filed: September 15, 2016
    Publication date: January 5, 2017
    Inventors: Violante Moschiano, Andrea D'Alessandro, Andrea Giovanni Xotta
  • BOOSTING CHANNELS OF MEMORY CELLS
    Publication number: 20160372201
    Abstract: A method for programming a non-volatile memory device includes concurrently boosting channels of memory cells in a selected memory string and an unselected memory string of the memory device, discharging the boosted channels of the memory cells in the selected memory string, and programming a selected memory cell in the selected memory string after discharging the boosted channels in the selected memory string.
    Type: Application
    Filed: June 16, 2015
    Publication date: December 22, 2016
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Violante Moschiano, Akira Goda, Mason A. Jones
  • Threshold voltage compensation in a memory
    Patent number: 9520183
    Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: December 13, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Tommaso Vali, Giovanni Naso, Vishal Sarin, William Henry Radke, Theodore T. Pekny
  • THRESHOLD VOLTAGE ANALYSIS
    Publication number: 20160358647
    Abstract: Apparatuses and methods for threshold voltage analysis are described. One or more methods for threshold voltage analysis include storing expected state indicators corresponding to a group of memory cells, applying a first sensing voltage to a selected access line to which the group of memory cells is coupled, sensing whether at least one of the memory cells of the group conducts responsive to the first sensing voltage, determining whether a discharge indicator for the at least one of the memory cells has changed responsive to application of the first sensing voltage, and determining that the first sensing voltage is the threshold voltage for a particular program state of the at least one of the memory cells.
    Type: Application
    Filed: August 23, 2016
    Publication date: December 8, 2016
    Inventors: William C. Filipiak, Violante Moschiano
  • Concurrently reading first and second pages of memory cells having different page addresses
    Patent number: 9502125
    Abstract: In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The second memory plane is different than the first memory plane, but is in the same memory array as the first memory plane. The second page of memory cells has a different page address than the first page of memory cells.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: November 22, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Mattia Cichocki, Tommaso Vali, Maria-Luisa Gallese, Umberto Siciliani
  • Methods of programming memory devices
    Patent number: 9490025
    Abstract: Methods of programming memory devices include biasing each data line of a plurality of data lines to a program inhibit voltage; discharging a first portion of data lines of the plurality of data lines, wherein the first portion of data lines of the plurality of data lines are coupled to memory cells selected for programming; and applying a plurality of programming pulses to the memory cells selected for programming while biasing a remaining portion of data lines of the plurality of data lines to the program inhibit voltage.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: November 8, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Andrew Bicksler, Violante Moschiano, Giuseppina Puzzilli
  • Methods of programming memories
    Patent number: 9484101
    Abstract: Methods of programming memories include applying a first plurality of programming pulses to the group of memory cells to program first data to the group of memory cells, determining an upper limit of a resulting threshold voltage distribution for the group of memory cells following a particular programming pulse of the first plurality of programming pulses, and applying a second plurality of programming pulses to the group of memory cells to program second data to the group of memory cells, wherein a characteristic of at least one of the programming pulses of the second plurality of programming pulses is at least partially based on the determined upper limit of the threshold voltage distribution. Methods of programming memories further include programming information indicative of usage of memory cells of a page of memory cells to the page of memory cells during a portion of a programming operation.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: November 1, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Pranav Kalavade, Akira Goda, Tommaso Vali, Violante Moschiano
  • Determining soft data
    Patent number: 9460783
    Abstract: The present application includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. In a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: October 4, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Andrea D'Alessandro, Andrea Giovanni Xotta
  • Threshold voltage analysis
    Patent number: 9455029
    Abstract: Apparatuses and methods for threshold voltage analysis are described. One or more methods for threshold voltage analysis include storing expected state indicators corresponding to a group of memory cells, applying a first sensing voltage to a selected access line to which the group of memory cells is coupled, sensing whether at least one of the memory cells of the group conducts responsive to the first sensing voltage, determining whether a discharge indicator for the at least one of the memory cells has changed responsive to application of the first sensing voltage, and determining that the first sensing voltage is the threshold voltage for a particular program state of the at least one of the memory cells.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: September 27, 2016
    Assignee: Micron Technology, Inc.
    Inventors: William C. Filipiak, Violante Moschiano
  • Dynamic program window determination in a memory device
    Patent number: 9455043
    Abstract: A memory device has a controller. The controller is configured to cause the memory device to inhibit programming of a group of memory cells. The controller is configured to cause the memory device to apply a programming pulse to control gates of the group of memory cells. The controller is configured to determine an amount of disturb experienced by the group of memory cells responsive to the programming pulse. The controller is configured to determine a program window responsive to the amount of disturb.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: September 27, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Tommaso Vali, Giovanni Santin, Massimo Rossini, William H. Radke, Violante Moschiano
  • HIGH PERFORMANCE MEMORY CONTROLLER
    Publication number: 20160266966
    Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).
    Type: Application
    Filed: March 13, 2015
    Publication date: September 15, 2016
    Inventors: Violante Moschiano, Walter Di Francesco, Luca De Santis, Giovanni Santin
  • APPARATUS AND METHODS FOR DETERMINING A PASS/FAIL CONDITION OF A MEMORY DEVICE
    Publication number: 20160211034
    Abstract: Memory devices including an array of memory cells, a first buffer selectively connected to the array of memory cells and corresponding to a particular bit rank of a byte of information of a programming operation of the memory device, and a second buffer selectively connected to the array of memory cells and corresponding to the particular bit rank of a different byte of information of the programming operation of the memory device, wherein an output of the first buffer and an output of the second buffer are connected in parallel to a common line, as well as methods of their operation to indicate a pass/fail condition of the programming operation.
    Type: Application
    Filed: March 30, 2016
    Publication date: July 21, 2016
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Violante Moschiano, Giovanni Santin