Patents by Inventor Viorel Ontalus
Viorel Ontalus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11916135Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor and methods of manufacture. The structure includes: a collector region in a semiconductor substrate; a base region adjacent to the collector region; and an emitter extending above the base region and comprising semiconductor material and a hardmask surrounding a lower portion of the semiconductor material.Type: GrantFiled: January 28, 2022Date of Patent: February 27, 2024Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Viorel Ontalus, Justin C. Long, Robert K. Baiocco
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Publication number: 20230395607Abstract: Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.Type: ApplicationFiled: June 2, 2022Publication date: December 7, 2023Inventors: Peter Baars, Viorel Ontalus, Ketankumar H. Tailor, Michael Zier, Crystal R. Kenney, Judson Holt
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Patent number: 11810951Abstract: Disclosed are a semiconductor structure and method of forming the structure. The structure includes a field effect transistor (FET) with a channel region between source/drain regions that extend through a semiconductor layer and into an insulator layer, that include a first portion in the insulator layer, and a second portion on the first portion in the semiconductor layer and, optionally, extending above the semiconductor layer. The first portion is relatively wide, includes a shallow section below the second portion, and a deep section adjacent to the channel region and overlayed by the semiconductor layer. The uniquely shaped first portion boosts saturation current to be boosted to allow the height of the second portion to be reduced to minimize overlap capacitance. Optionally, each source/drain region includes multiple semiconductor materials including a stress-inducing semiconductor material grown laterally from the semiconductor layer to improve charge carrier mobility in the channel region.Type: GrantFiled: December 16, 2021Date of Patent: November 7, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Jianwei Peng, Hong Yu, Viorel Ontalus
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Publication number: 20230246093Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor and methods of manufacture. The structure includes: a collector region in a semiconductor substrate; a base region adjacent to the collector region; and an emitter extending above the base region and comprising semiconductor material and a hardmask surrounding a lower portion of the semiconductor material.Type: ApplicationFiled: January 28, 2022Publication date: August 3, 2023Inventors: Viorel ONTALUS, Justin C. LONG, Robert K. BAIOCCO
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Publication number: 20230197783Abstract: Disclosed are a semiconductor structure and method of forming the structure. The structure includes a field effect transistor (FET) with a channel region between source/drain regions that extend through a semiconductor layer and into an insulator layer, that include a first portion in the insulator layer, and a second portion on the first portion in the semiconductor layer and, optionally, extending above the semiconductor layer. The first portion is relatively wide, includes a shallow section below the second portion, and a deep section adjacent to the channel region and overlayed by the semiconductor layer. The uniquely shaped first portion boosts saturation current to be boosted to allow the height of the second portion to be reduced to minimize overlap capacitance. Optionally, each source/drain region includes multiple semiconductor materials including a stress-inducing semiconductor material grown laterally from the semiconductor layer to improve charge carrier mobility in the channel region.Type: ApplicationFiled: December 16, 2021Publication date: June 22, 2023Applicant: GlobalFoundries U.S. Inc.Inventors: Jianwei Peng, Hong Yu, Viorel Ontalus
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Patent number: 11217685Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a device with a marker layer and methods of manufacture. The device includes: a collector region; an intrinsic base region above the collector region; an emitter region comprising emitter material and a marker layer vertically between the intrinsic base region and the emitter material; and an extrinsic base region in electrical contact with the intrinsic base region.Type: GrantFiled: June 23, 2020Date of Patent: January 4, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Herbert Ho, Vibhor Jain, John J. Pekarik, Claude Ortolland, Judson R. Holt, Qizhi Liu, Viorel Ontalus
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Patent number: 11056533Abstract: One illustrative device disclosed herein includes a semiconductor substrate, a bipolar junction transistor (BJT) device that comprises a collector, a base and an emitter, at least one piezoelectric structure comprising a piezoelectric material positioned adjacent the BJT device, and at least first and second conductive contact structures that are conductively coupled to the piezoelectric structure.Type: GrantFiled: February 28, 2020Date of Patent: July 6, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventor: Viorel Ontalus
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Publication number: 20210091214Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a device with a marker layer and methods of manufacture. The device includes: a collector region; an intrinsic base region above the collector region; an emitter region comprising emitter material and a marker layer vertically between the intrinsic base region and the emitter material; and an extrinsic base region in electrical contact with the intrinsic base region.Type: ApplicationFiled: June 23, 2020Publication date: March 25, 2021Inventors: Herbert HO, Vibhor JAIN, John J. PEKARIK, Claude ORTOLLAND, Judson R. HOLT, Qizhi LIU, Viorel ONTALUS
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Patent number: 10374090Abstract: After forming an epitaxial semiconductor layer on portions of a semiconductor located on opposite sides of a sacrificial gate structure, dopants from the epitaxial semiconductor layer are diffused into the semiconductor fin to form a dopant-containing semiconductor fin. A sacrificial gate stack is removed to provide a gate cavity that exposes a portion of the dopant-containing semiconductor fin. The exposed portion of the dopant-containing semiconductor fin is removed to provide an opening underneath the gate cavity. A channel which is undoped or less doped than remaining portions of the dopant-containing semiconductor fin is epitaxially grown at least from the sidewalls of the remaining portions of the dopant-containing semiconductor fin. Abrupt junctions are thus formed between the channel region and the remaining portions of the dopant-containing semiconductor fin.Type: GrantFiled: August 14, 2017Date of Patent: August 6, 2019Assignee: GLOBALFOUNDRIES INC.Inventor: Viorel Ontalus
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Publication number: 20180197734Abstract: Reducing wormhole formation during n-type transistor fabrication includes providing a starting structure, the starting structure including a semiconductor substrate, a n-type source region and a n-type drain region of a transistor. The method further includes removing a portion of each of the n-type source region and the n-type drain region, the removing creating a source trench and a drain trench, and forming a buffer layer of silicon-based material(s) over the n-type source region and n-type drain region that is sufficiently thick to inhibit interaction between metal contaminants that may be present below surfaces of the n-type source trench and/or the n-type drain trench, and halogens subsequently introduced prior to source and drain formation. A resulting semiconductor structure is also provided.Type: ApplicationFiled: January 12, 2017Publication date: July 12, 2018Applicant: GLOBALFOUNDRIES Inc.Inventors: Bhupesh CHANDRA, Annie LEVESQUE, Matthew W. STOKER, Shreesh NARASIMHA, Viorel ONTALUS, Michael STEIGERWALT, Joshua BELL
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Patent number: 9953873Abstract: Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.Type: GrantFiled: May 24, 2016Date of Patent: April 24, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Bhupesh Chandra, Claude Ortolland, Gregory G. Freeman, Viorel Ontalus, Christopher D. Sheraw, Timothy J. McArdle, Paul Chang
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Publication number: 20170345719Abstract: Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.Type: ApplicationFiled: May 24, 2016Publication date: November 30, 2017Inventors: Bhupesh Chandra, Claude Ortolland, Gregory G. Freeman, Viorel Ontalus, Christopher D. Sheraw, Timothy J. McArdle, Paul Chang
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Publication number: 20170345934Abstract: After forming an epitaxial semiconductor layer on portions of a semiconductor located on opposite sides of a sacrificial gate structure, dopants from the epitaxial semiconductor layer are diffused into the semiconductor fin to form a dopant-containing semiconductor fin. A sacrificial gate stack is removed to provide a gate cavity that exposes a portion of the dopant-containing semiconductor fin. The exposed portion of the dopant-containing semiconductor fin is removed to provide an opening underneath the gate cavity. A channel which is undoped or less doped than remaining portions of the dopant-containing semiconductor fin is epitaxially grown at least from the sidewalls of the remaining portions of the dopant-containing semiconductor fin. Abrupt junctions are thus formed between the channel region and the remaining portions of the dopant-containing semiconductor fin.Type: ApplicationFiled: August 14, 2017Publication date: November 30, 2017Applicant: GLOBALFOUNDRIES INC.Inventor: Viorel Ontalus
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Patent number: 9761720Abstract: After forming an epitaxial semiconductor layer on portions of a semiconductor located on opposite sides of a sacrificial gate structure, dopants from the epitaxial semiconductor layer are diffused into the semiconductor fin to form a dopant-containing semiconductor fin. A sacrificial gate stack is removed to provide a gate cavity that exposes a portion of the dopant-containing semiconductor fin. The exposed portion of the dopant-containing semiconductor fin is removed to provide an opening underneath the gate cavity. A channel which is undoped or less doped than remaining portions of the dopant-containing semiconductor fin is epitaxially grown at least from the sidewalls of the remaining portions of the dopant-containing semiconductor fin. Abrupt junctions are thus formed between the channel region and the remaining portions of the dopant-containing semiconductor fin.Type: GrantFiled: November 30, 2015Date of Patent: September 12, 2017Assignee: GLOBALFOUNDRIES INC.Inventor: Viorel Ontalus
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Patent number: 9722045Abstract: The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.Type: GrantFiled: October 23, 2015Date of Patent: August 1, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Bhupesh Chandra, Viorel Ontalus, Timothy J. McArdle, Paul Chang, Claude Ortolland, Judson R. Holt
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Publication number: 20170154995Abstract: After forming an epitaxial semiconductor layer on portions of a semiconductor located on opposite sides of a sacrificial gate structure, dopants from the epitaxial semiconductor layer are diffused into the semiconductor fin to form a dopant-containing semiconductor fin. A sacrificial gate stack is removed to provide a gate cavity that exposes a portion of the dopant-containing semiconductor fin. The exposed portion of the dopant-containing semiconductor fin is removed to provide an opening underneath the gate cavity. A channel which is undoped or less doped than remaining portions of the dopant-containing semiconductor fin is epitaxially grown at least from the sidewalls of the remaining portions of the dopant-containing semiconductor fin. Abrupt junctions are thus formed between the channel region and the remaining portions of the dopant-containing semiconductor fin.Type: ApplicationFiled: November 30, 2015Publication date: June 1, 2017Applicant: GLOBALFOUNDRIES INC.Inventor: Viorel Ontalus
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Publication number: 20170117387Abstract: The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.Type: ApplicationFiled: October 23, 2015Publication date: April 27, 2017Inventors: Bhupesh Chandra, Viorel Ontalus, Timothy J. McArdle, Paul Chang, Claude Ortolland, Judson R. Holt
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Patent number: 9536989Abstract: Device structures and fabrication methods for a fin-type field-effect transistor. A first fin and a second fin are formed that are comprised of a semiconductor material that is single crystal. The first fin has a sidewall facing a sidewall of the second fin. A portion of a source/drain region of the first fin is damaged to form a damage region in the portion of the first fin. After the damage region is formed, a section of a semiconductor layer is epitaxially grown from the sidewall of the first fin in the source/drain region. The semiconductor material in the damage region has a level of crystalline disorder that is greater than a level of crystalline disorder of the semiconductor material in a portion of the first fin that is not damaged.Type: GrantFiled: February 15, 2016Date of Patent: January 3, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Viorel Ontalus, Annie Lévesque
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Patent number: 9385237Abstract: Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface portions of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions can be deposited as layers and subsequently patterned by etching, or can be formed after formation of disposable masking spacers. Raised source and drain regions are formed on the carbon-doped semiconductor material portions and on physically exposed surfaces of the underlying semiconductor surfaces.Type: GrantFiled: April 15, 2015Date of Patent: July 5, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pranita Kerber, Viorel Ontalus, Donald R. Wall, Zhengmao Zhu
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Patent number: 9349749Abstract: A semiconductor device comprises first and second gate stacks formed on a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a dielectric layer interposed between a bulk substrate layer and an active semiconductor layer. A first extension implant portion is disposed adjacent to the first gate stack and a second extension implant portion is disposed adjacent to the second gate stack. A halo implant extends continuously about the trench. A butting implant extends between the trench and the dielectric layer. An epitaxial layer is formed at the exposed region such that the butting implant is interposed between the epitaxial layer and the dielectric layer.Type: GrantFiled: August 21, 2015Date of Patent: May 24, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Viorel Ontalus, Robert R. Robison, Xin Wang