Patents by Inventor Vishal C. Aslot

Vishal C. Aslot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11210282
    Abstract: For improving data placement optimization in a computing storage environment, an application layer and/or a user are allowed to attach anticipated usage metadata and directive metadata to a file. The anticipated usage metadata contains a plurality of attributes describing characteristics of the file and the directive metadata contains directives comprising storage instructions for the file. Additionally, a set of metadata is added to the file at a time of creation. The core metadata includes characteristics such as an importance factor as to how essential the anticipated usage metadata and directive metadata should be followed when determining file placement with the computing storage environment.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: December 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vishal C. Aslot, Adekunle Bello, Gregory J. Boss
  • Patent number: 11036431
    Abstract: A system for generating memory references is provided. Instructions to perform a memory data operation on a database from a computer system is received. A computing system generates a memory reference in a region of memory, wherein the memory reference is independent of where the memory is accessible by a computing system. A memory reference to a memory region on a database is stored by a computing system. A memory reference based, at least, on the memory data operation is translated. A data in the memory via the instruction to perform a memory data operation is accessed. A memory data from the database is retrieved.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: June 15, 2021
    Assignee: International Business Machines Corporation
    Inventors: Vishal C. Aslot, Anil Kalavakolanu, Brian W. Hart, Evan Allen Zoss
  • Publication number: 20200409595
    Abstract: A system for generating memory references is provided. Instructions to perform a memory data operation on a database from a computer system is received. A computing system generates a memory reference in a region of memory, wherein the memory reference is independent of where the memory is accessible by a computing system. A memory reference to a memory region on a database is stored by a computing system. A memory reference based, at least, on the memory data operation is translated. A data in the memory via the instruction to perform a memory data operation is accessed. A memory data from the database is retrieved.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 31, 2020
    Inventors: Vishal C. Aslot, Anil Kalavakolanu, Brian W. Hart, Evan Allen Zoss
  • Patent number: 10671369
    Abstract: The present disclosure relates to updating a firmware image on a coherent hardware accelerator concurrently with executing operations on the coherent hardware accelerator. According to one embodiment, while executing accelerator-enabled operations on the coherent hardware accelerator, a system stores a firmware update package in a local memory on the coherent hardware accelerator. Once the firmware update package is stored in local memory on the coherent hardware accelerator, the system restarting the coherent hardware accelerator by pausing the execution of at least a first operation initiated on the coherent hardware accelerator and applying the firmware update package to the firmware image on the coherent hardware accelerator. Once the firmware update package is applied to the coherent hardware accelerator, the system resumes the operation on the coherent hardware accelerator.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andre L. Albot, Vishal C. Aslot, Thomas V. Burks, III, John D. Dietel
  • Patent number: 10620932
    Abstract: The present disclosure relates to updating a firmware image on a coherent hardware accelerator concurrently with executing operations on the coherent hardware accelerator. According to one embodiment, while executing accelerator-enabled operations on the coherent hardware accelerator, a system stores a firmware update package in a local memory on the coherent hardware accelerator. Once the firmware update package is stored in local memory on the coherent hardware accelerator, the system restarting the coherent hardware accelerator by pausing the execution of at least a first operation initiated on the coherent hardware accelerator and applying the firmware update package to the firmware image on the coherent hardware accelerator. Once the firmware update package is applied to the coherent hardware accelerator, the system resumes the operation on the coherent hardware accelerator.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andre L. Albot, Vishal C. Aslot, Thomas V. Burks, III, John D. Dietel
  • Patent number: 10303882
    Abstract: A method and apparatus are provided for implementing system locale management including locale replacement risk analysis in a computer system. A Locale Update Risk Analysis Agent (RAA) scans globalization API usages on each pair of locale and running application. The scanned API list of each running application is compared with predefined API locale sensitive weights, and a locale replacement risk index is calculated on each application under a certain locale. A living locale-object update decision is made based on the calculated locale replacement risk indexes.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Debbie A. Anglin, Vishal C. Aslot, Yu Gu, Su Liu
  • Patent number: 10157145
    Abstract: Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. A request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: December 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Andre L. Albot, Vishal C. Aslot, Mark Rogers, Randal C. Swanberg
  • Patent number: 10157144
    Abstract: Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. A request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: December 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Andre L. Albot, Vishal C. Aslot, Mark Rogers, Randal C. Swanberg
  • Publication number: 20180336238
    Abstract: For improving data placement optimization in a computing storage environment, an application layer and/or a user are allowed to attach anticipated usage metadata and directive metadata to a file. The anticipated usage metadata contains a plurality of attributes describing characteristics of the file and the directive metadata contains directives comprising storage instructions for the file. Additionally, a set of metadata is added to the file at a time of creation. The core metadata includes characteristics such as an importance factor as to how essential the anticipated usage metadata and directive metadata should be followed when determining file placement with the computing storage environment.
    Type: Application
    Filed: July 30, 2018
    Publication date: November 22, 2018
    Inventors: Vishal C. ASLOT, Adekunle BELLO, Gregory J. BOSS
  • Publication number: 20180322290
    Abstract: A method and apparatus are provided for implementing system locale management including locale replacement risk analysis in a computer system. A Locale Update Risk Analysis Agent (RAA) scans globalization API usages on each pair of locale and running application. The scanned API list of each running application is compared with predefined API locale sensitive weights, and a locale replacement risk index is calculated on each application under a certain locale. A living locale-object update decision is made based on the calculated locale replacement risk indexes.
    Type: Application
    Filed: July 10, 2018
    Publication date: November 8, 2018
    Inventors: Debbie A. Anglin, Vishal C. Aslot, Yu Gu, Su Liu
  • Patent number: 10120891
    Abstract: For improving data placement optimization in a computing storage environment, an application layer and/or a user are allowed to attach anticipated usage metadata and directive metadata to a file.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: November 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vishal C. Aslot, Adekunle Bello, Gregory J. Boss
  • Patent number: 10102376
    Abstract: A method and apparatus are provided for implementing system locale management including locale replacement risk analysis in a computer system. A Locale Update Risk Analysis Agent (RAA) scans globalization API usages on each pair of locale and running application. The scanned API list of each running application is compared with predefined API locale sensitive weights, and a locale replacement risk index is calculated on each application under a certain locale. A living locale-object update decision is made based on the calculated locale replacement risk indexes.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: October 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Debbie A. Anglin, Vishal C. Aslot, Yu Gu, Su Liu
  • Patent number: 10057289
    Abstract: A system and method and computer program product for user authentication that uses information about a user's context or context of their personal device(s) to dynamically modify that user's authentication or login requirements to an application in a computer or mobile device. The system is configured to run methods that detect and make use of a user's context that includes: a current environment or personal context, and uses this capability to enable variable strength authentication when attempting to log in or enter another application or resource. In one embodiment, the system implements methods to dynamically adjust the authentication challenge as a differential of all accumulated user contexts (e.g., providing a shorter password or pin-code).
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: August 21, 2018
    Assignee: International Business Machines Corporation
    Inventors: Tamer E. Abuelsaad, Vishal C. Aslot, Adekunle Bello, Gregory J. Boss
  • Patent number: 10031858
    Abstract: Methods to perform an operation comprising identifying, in a software page frame table by an operating system interrupt handler, a physical address of a memory page, wherein the physical address of the memory page is identified based on a virtual segment identifier (VSID) and a page number, wherein the VSID is specified in an interrupt received from a coherent accelerator and wherein the coherent accelerator generated the interrupt in response to a page fault associated with the memory page, and creating, by the operating system interrupt handler, a page table entry in a hardware page table associating the VSID and the page number with the physical address of the memory page, wherein creating the page table entry resolves the page fault.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Vishal C. Aslot, Arnold Flores, Mark D. Rogers
  • Patent number: 10025722
    Abstract: Systems and computer program products to perform an operation comprising identifying, in a software page frame table by an operating system interrupt handler, a physical address of a memory page, wherein the physical address of the memory page is identified based on a virtual segment identifier (VSID) and a page number, wherein the VSID is specified in an interrupt received from a coherent accelerator and wherein the coherent accelerator generated the interrupt in response to a page fault associated with the memory page, and creating, by the operating system interrupt handler, a page table entry in a hardware page table associating the VSID and the page number with the physical address of the memory page, wherein creating the page table entry resolves the page fault.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Vishal C. Aslot, Arnold Flores, Mark D. Rogers
  • Patent number: 9996357
    Abstract: Systems, methods, and computer program products to perform an operation comprising creating, by a kernel, a temporary effective address associated with a virtual segment identifier (VSID), wherein the VSID is received by a processor in an asynchronous interrupt generated by a coherent accelerator in response to a page fault generated by the coherent accelerator in executing an instruction, accessing the temporary effective address by the processor to recreate the page fault on the processor, and resolving the page fault by an operating system executing on the processor.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andre L. Albot, Vishal C. Aslot, Arnold Flores, Bruce Mealey, Mark D. Rogers
  • Patent number: 9971550
    Abstract: A processor-implemented method for copying a source file to a destination file using a virtual memory manager (VMM) of a computer operating system is provided. The method includes receiving, by the VMM, a request to copy the source file to a destination file. The method further provides that based on the status of the virtual page, performing at least one of moving the virtual page to the destination file, copying the virtual page to the destination file, reading the virtual page into memory, and ignoring the virtual page.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Vishal C. Aslot, Ninad S. Palsule
  • Patent number: 9971701
    Abstract: Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. According to one embodiment, a request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: May 15, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andre L. Albot, Vishal C. Aslot, Mark D. Rogers, Randal C. Swanberg
  • Publication number: 20180129609
    Abstract: Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. A request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.
    Type: Application
    Filed: January 3, 2018
    Publication date: May 10, 2018
    Inventors: Andre L. ALBOT, Vishal C. ASLOT, Mark ROGERS, Randal C. SWANBERG
  • Publication number: 20180129610
    Abstract: Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. A request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.
    Type: Application
    Filed: January 4, 2018
    Publication date: May 10, 2018
    Inventors: Andre L. ALBOT, Vishal C. ASLOT, Mark ROGERS, Randal C. SWANBERG