Patents by Inventor Vishal C. Aslot

Vishal C. Aslot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170132083
    Abstract: Systems, methods, and computer program products to perform an operation comprising determining, by a processor, a process identifier of a process associated with a page fault based on an interrupt source number, wherein the page fault was triggered by a coherent accelerator, executing the process on the processor to recreate the page fault on the processor, and resolving the page fault by an operating system executing on the processor.
    Type: Application
    Filed: November 10, 2015
    Publication date: May 11, 2017
    Inventors: Vishal C. ASLOT, Bruce MEALEY, Mark D. ROGERS, Randal C. SWANBERG
  • Publication number: 20170132032
    Abstract: Embodiments disclose techniques for enabling the use poll and select subroutines with coherent accelerator block or character devices. In one embodiment, an operating system receives, from an application, a system call to attach a hardware context with the coherent accelerator block or character device. The operating system generates a channel based on a file descriptor associated with the attach system call. The operating system associates the channel with a hardware context selected from a plurality of hardware contexts available to the coherent accelerator, wherein the hardware context is attached to the application. Upon receiving, from the application, a system call to check for exceptions that have occurred on the coherent accelerator block device or character device, the operating system returns an indication of any exceptions which have occurred while the coherent accelerator was using the hardware context to the application.
    Type: Application
    Filed: November 10, 2015
    Publication date: May 11, 2017
    Inventors: Vishal C. ASLOT, Bruce MEALEY, Grover H. NEUMAN, Randal C. SWANBERG
  • Publication number: 20170123997
    Abstract: Methods to perform an operation comprising identifying, in a software page frame table by an operating system interrupt handler, a physical address of a memory page, wherein the physical address of the memory page is identified based on a virtual segment identifier (VSID) and a page number, wherein the VSID is specified in an interrupt received from a coherent accelerator and wherein the coherent accelerator generated the interrupt in response to a page fault associated with the memory page, and creating, by the operating system interrupt handler, a page table entry in a hardware page table associating the VSID and the page number with the physical address of the memory page, wherein creating the page table entry resolves the page fault.
    Type: Application
    Filed: January 4, 2016
    Publication date: May 4, 2017
    Inventors: Vishal C. Aslot, Arnold Flores, Mark D. Rogers
  • Publication number: 20170123684
    Abstract: Embodiments disclose techniques for emulating memory mapped I/O (MMIO) for coherent accelerators in an error state. In one embodiment, once an operating system determines that a processor is unable to access a coherent accelerator via a MMIO operation, the operating system deletes one or more page table entries associated with MMIO of one or more hardware contexts of the coherent accelerator. After deleting the page table entries, the operating system can detect a page fault associated with execution of a process by the processor. Upon determining that the page fault was caused by the process attempting to access one of the deleted page table entries while executing a MMIO operation, the operating system emulates the execution of the MMIO operation for the faulting process, giving the process the illusion that its requested MMIO operation was successful.
    Type: Application
    Filed: November 3, 2015
    Publication date: May 4, 2017
    Inventors: Andre L. ALBOT, Vishal C. ASLOT, Bruce MEALEY, Nicholas STILWELL
  • Publication number: 20170123779
    Abstract: The present disclosure relates to updating a firmware image on a coherent hardware accelerator concurrently with executing operations on the coherent hardware accelerator. According to one embodiment, while executing accelerator-enabled operations on the coherent hardware accelerator, a system stores a firmware update package in a local memory on the coherent hardware accelerator. Once the firmware update package is stored in local memory on the coherent hardware accelerator, the system restarting the coherent hardware accelerator by pausing the execution of at least a first operation initiated on the coherent hardware accelerator and applying the firmware update package to the firmware image on the coherent hardware accelerator. Once the firmware update package is applied to the coherent hardware accelerator, the system resumes the operation on the coherent hardware accelerator.
    Type: Application
    Filed: October 28, 2015
    Publication date: May 4, 2017
    Inventors: Andre L. ALBOT, Vishal C. ASLOT, Thomas V. BURKS, III, John D. DIETEL
  • Publication number: 20170123780
    Abstract: The present disclosure relates to updating a firmware image on a coherent hardware accelerator concurrently with executing operations on the coherent hardware accelerator. According to one embodiment, while executing accelerator-enabled operations on the coherent hardware accelerator, a system stores a firmware update package in a local memory on the coherent hardware accelerator. Once the firmware update package is stored in local memory on the coherent hardware accelerator, the system restarting the coherent hardware accelerator by pausing the execution of at least a first operation initiated on the coherent hardware accelerator and applying the firmware update package to the firmware image on the coherent hardware accelerator. Once the firmware update package is applied to the coherent hardware accelerator, the system resumes the operation on the coherent hardware accelerator.
    Type: Application
    Filed: January 4, 2016
    Publication date: May 4, 2017
    Inventors: Andre L. ALBOT, Vishal C. ASLOT, Thomas V. BURKS, III, John D. DIETEL
  • Publication number: 20170123999
    Abstract: Systems and computer program products to perform an operation comprising identifying, in a software page frame table by an operating system interrupt handler, a physical address of a memory page, wherein the physical address of the memory page is identified based on a virtual segment identifier (VSID) and a page number, wherein the VSID is specified in an interrupt received from a coherent accelerator and wherein the coherent accelerator generated the interrupt in response to a page fault associated with the memory page, and creating, by the operating system interrupt handler, a page table entry in a hardware page table associating the VSID and the page number with the physical address of the memory page, wherein creating the page table entry resolves the page fault.
    Type: Application
    Filed: October 28, 2015
    Publication date: May 4, 2017
    Inventors: Vishal C. ASLOT, Arnold FLORES, Mark D. ROGERS
  • Publication number: 20170123690
    Abstract: Systems, methods, and computer program products to perform an operation comprising creating, by a kernel, a temporary effective address associated with a virtual segment identifier (VSID), wherein the VSID is received by a processor in an asynchronous interrupt generated by a coherent accelerator in response to a page fault generated by the coherent accelerator in executing an instruction, accessing the temporary effective address by the processor to recreate the page fault on the processor, and resolving the page fault by an operating system executing on the processor.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Inventors: Andre L. Albot, Vishal C. Aslot, Arnold Flores, Bruce Mealey, Mark D. Rogers
  • Publication number: 20170109290
    Abstract: Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. According to one embodiment, a request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.
    Type: Application
    Filed: October 16, 2015
    Publication date: April 20, 2017
    Inventors: Andre L. ALBOT, Vishal C. ASLOT, Mark D. ROGERS, Randal C. SWANBERG
  • Publication number: 20170109291
    Abstract: Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. According to one embodiment, a request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.
    Type: Application
    Filed: January 4, 2016
    Publication date: April 20, 2017
    Inventors: Andre L. ALBOT, Vishal C. ASLOT, Mark D. ROGERS, Randal C. SWANBERG
  • Patent number: 9563361
    Abstract: A processor-implemented method for copying a source file to a destination file using a virtual memory manager (VMM) of a computer operating system is provided. The method includes receiving, by the VMM, a request to copy the source file to a destination file. The method further provides that based on the status of the virtual page, performing at least one of moving the virtual page to the destination file, copying the virtual page to the destination file, reading the virtual page into memory, and ignoring the virtual page.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Vishal C. Aslot, Ninad S. Palsule
  • Patent number: 9424082
    Abstract: A method, system and computer-usable medium are disclosed for startup page fault management improves application startup performance by assigning startup tasks to a hardware thread 0 across plural processing cores in a simultaneous multithreading environment to provide more rapid processing of processor bound page faults. I/O bound page faults are flagged to associated with predetermined cache locations to improve data and text first reference page-in I/O response.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: August 23, 2016
    Assignee: International Business Machines Corporation
    Inventors: Vishal C. Aslot, Adekunle Bello, Gunisha Madan
  • Patent number: 9411638
    Abstract: A method, system and computer-usable medium are disclosed for startup page fault management improves application startup performance by assigning startup tasks to a hardware thread 0 across plural processing cores in a simultaneous multithreading environment to provide more rapid processing of processor bound page faults. I/O bound page faults are flagged to associated with predetermined cache locations to improve data and text first reference page-in I/O response.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: August 9, 2016
    Assignee: International Business Machines Corporation
    Inventors: Vishal C. Aslot, Adekunle Bello, Gunisha Madan
  • Publication number: 20160162413
    Abstract: A method, system and computer-usable medium are disclosed for startup page fault management improves application startup performance by assigning startup tasks to a hardware thread 0 across plural processing cores in a simultaneous multithreading environment to provide more rapid processing of processor bound page faults. I/O bound page faults are flagged to associated with predetermined cache locations to improve data and text first reference page-in I/O response.
    Type: Application
    Filed: February 10, 2016
    Publication date: June 9, 2016
    Inventors: Vishal C. Aslot, Adekunle Bello, Gunisha Madan
  • Patent number: 9342342
    Abstract: According to one aspect of the present disclosure a system and technique for refreshing memory topology in virtual machine operating systems is disclosed. The system includes a processor and logic executable by the processor to: responsive to receiving, by an operating system of a virtual machine, a notification of an affinity change relative to workload memory resources, poll a hypervisor for updated memory affinity data; determine, for each logical memory block of the workload memory resources, whether an affinity string for the respective logical memory block has changed; responsive to determining that the affinity string for the respective logical memory block has changed, identify a data structure of the logical memory block maintained by the operating system; and update affinity information in the data structure based on the change to the affinity string of the logical memory block.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 17, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vishal C. Aslot, Arnold Flores, Mark D. Rogers
  • Patent number: 9336038
    Abstract: According to one aspect of the present disclosure, a method and technique for refreshing memory topology in virtual machine operating systems is disclosed. The method includes: responsive to receiving, by an operating system of a virtual machine, a notification of an affinity change relative to workload memory resources, polling a hypervisor for updated memory affinity data; determining, for each logical memory block of the workload memory resources, whether an affinity string for the respective logical memory block has changed; responsive to determining that the affinity string for the respective logical memory block has changed, identifying a data structure of the logical memory block maintained by the operating system; and updating affinity information in the data structure based on the change to the affinity string of the logical memory block.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: May 10, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vishal C. Aslot, Arnold Flores, Mark D. Rogers
  • Publication number: 20150178219
    Abstract: A method, system and computer-usable medium are disclosed for startup page fault management improves application startup performance by assigning startup tasks to a hardware thread 0 across plural processing cores in a simultaneous multithreading environment to provide more rapid processing of processor bound page faults. I/O bound page faults are flagged to associated with predetermined cache locations to improve data and text first reference page-in I/O response.
    Type: Application
    Filed: December 19, 2013
    Publication date: June 25, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vishal C. Aslot, Adekunle Bello, Gunisha Madan
  • Patent number: 8984240
    Abstract: Page faults during partition migration from a source computing system to a destination computing system are reduced by assigning each page used by a process as being hot or cold according to their frequency of use by the process. During a live partition migration, the cold or coldest (least frequently used) pages are copied to the destination server first, followed copying the warmer (less frequently used) and concluded by copying the hottest (most frequently used) pages. After all dirtied pages have been refreshed, cutover from the instance on the source server to the destination server is made. By transferring the warm and hot pages last (or later) in the migration process, the number of dirtied pages is reduced, thereby reducing page faults subsequent to the cutover.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Vishal C. Aslot, Adekunle Bello, Brian W. Hart
  • Publication number: 20150046969
    Abstract: A system and method and computer program product for user authentication that uses information about a user's context or context of their personal device(s) to dynamically modify that user's authentication or login requirements to an application in a computer or mobile device. The system is configured to run methods that detect and make use of a user's context that includes: a current environment or personal context, and uses this capability to enable variable strength authentication when attempting to log in or enter another application or resource. In one embodiment, the system implements methods to dynamically adjust the authentication challenge as a differential of all accumulated user contexts (e.g., providing a shorter password or pin-code).
    Type: Application
    Filed: August 12, 2013
    Publication date: February 12, 2015
    Applicant: International Business Machines Corporation
    Inventors: Tamer E. Abuelsaad, Vishal C. Aslot, Adekunle Bello, Gregory J. Boss
  • Publication number: 20140282515
    Abstract: According to one aspect of the present disclosure a system and technique for refreshing memory topology in virtual machine operating systems is disclosed. The system includes a processor and logic executable by the processor to: responsive to receiving, by an operating system of a virtual machine, a notification of an affinity change relative to workload memory resources, poll a hypervisor for updated memory affinity data; determine, for each logical memory block of the workload memory resources, whether an affinity string for the respective logical memory block has changed; responsive to determining that the affinity string for the respective logical memory block has changed, identify a data structure of the logical memory block maintained by the operating system; and update affinity information in the data structure based on the change to the affinity string of the logical memory block.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vishal C. Aslot, Arnold Flores, Mark D. Rogers