Patents by Inventor Vishnu K. Agarwal
Vishnu K. Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8120083Abstract: Apparatus and systems may comprise electrode structures that include two or more dissimilar and abutting metal layers on a surface, some of the electrode structures separated by a gap; and a polymer-based ferroelectric layer overlying and directly abutting some of the electrode structures. Methods may comprise actions to form and operate the apparatus and systems. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: July 30, 2010Date of Patent: February 21, 2012Assignee: Micron Technology, Inc.Inventors: Vishnu K. Agarwal, Howard E. Rhodes
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Patent number: 8111965Abstract: A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.Type: GrantFiled: May 2, 2011Date of Patent: February 7, 2012Assignee: Micron Technology, Inc.Inventors: Guy T. Blalock, Howard E. Rhodes, Vishnu K. Agarwal, Gurtej Singh Sandhu, James S. Foresi, Jean-Francois Viens, Dale G. Fried
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Publication number: 20110206332Abstract: A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.Type: ApplicationFiled: May 2, 2011Publication date: August 25, 2011Inventors: Guy T. Blalock, Howard E. Rhodes, Vishnu K. Agarwal, Gurtel Singh Sandhu, James S. Foresi, Jean-Francois Viens, Dale G. Fried
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Patent number: 7936955Abstract: A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.Type: GrantFiled: May 14, 2010Date of Patent: May 3, 2011Assignee: Micron Technology, Inc.Inventors: Guy T. Blalock, Howard E. Rhodes, Vishnu K. Agarwal, Gurtej Singh Sandhu, James S. Foresi, Jean-Francois Viens, Dale G. Fried
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Publication number: 20100290265Abstract: Apparatus and systems may comprise electrode structures that include two or more dissimilar and abutting metal layers on a surface, some of the electrode structures separated by a gap; and a polymer-based ferroelectric layer overlying and directly abutting some of the electrode structures. Methods may comprise actions to form and operate the apparatus and systems. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: July 30, 2010Publication date: November 18, 2010Inventors: Vishnu K. Agarwal, Howard E. Rhodes
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Publication number: 20100220958Abstract: A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.Type: ApplicationFiled: May 14, 2010Publication date: September 2, 2010Inventors: Guy T. Blalock, Howard E. Rhodes, Vishnu K. Agarwal, Gurtej Singh Sandhu, James S. Foresi, Jean-Francois Viens, Dale G. Fried
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Patent number: 7768049Abstract: Integrated memory circuits, key components in thousands of electronic and computer products, have been made using ferroelectric materials, which offer faster write cycles and lower power requirements than some other materials. However, the present inventors have recognized, for example, that conventional techniques for working with the polymers produce polymer layers with thickness variations that compromise performance and manufacturing yield. Accordingly, the present inventors devised unique methods and structures for polymer-based ferroelectric memories. One exemplary method entails forming an insulative layer on a substrate, forming two or more first conductive structures, with at least two of the first conductive structures separated by a gap, forming a gap-filling structure within the gap, and forming a polymer-based ferroelectric layer over the gap-filling structure and the first conductive structures. In some embodiments, the gap-filling structure is a polymer, a spin-on-glass, or a flow-fill oxide.Type: GrantFiled: August 30, 2005Date of Patent: August 3, 2010Assignee: Micron Technology, Inc.Inventors: Vishnu K. Agarwal, Howard E. Rhodes
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Patent number: 7720341Abstract: A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.Type: GrantFiled: March 13, 2008Date of Patent: May 18, 2010Assignee: Micron Technology, Inc.Inventors: Guy T. Blalock, Howard E. Rhodes, Vishnu K. Agarwal, Gurtej Singh Sandhu, James S. Foresi, Jean-Francois Viens, Dale G. Fried
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Patent number: 7548667Abstract: The present technique relates to a device including an optical integrated circuit amplifier and another type of optical integrated circuit. The optical integrated circuit amplifiers and other optical integrated circuits are coupled together through optical paths. The optical integrated circuit amplifiers and other optical integrated circuits of the optical components are fabricated on the same substrate. The optical integrated circuit amplifiers and other optical integrated circuit amplifiers maybe fabricated on different levels of the same substrate.Type: GrantFiled: September 24, 2007Date of Patent: June 16, 2009Assignee: Micron Technology, Inc.Inventor: Vishnu K. Agarwal
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Patent number: 7508074Abstract: In accordance with one embodiment of the present invention, a semiconductor structure is provided comprising a poly-metal stack formed over a semiconductor substrate where the interface between an oxidation barrier placed over the stack and an oxidized portion of the stack lies along the sidewall of the poly. The present invention also relates to a memory cell array comprising an array of wordlines and digitlines arranged to access respective memory cells within the array. Respective wordlines comprise a poly-metal stack formed over a semiconductor substrate in accordance with the present invention. Additionally, the present invention relates to a computer system comprising a memory cell array of the present invention.Type: GrantFiled: August 18, 2004Date of Patent: March 24, 2009Assignee: Micron Technology, Inc.Inventor: Vishnu K. Agarwal
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Patent number: 7508075Abstract: A semiconductor structure is provided comprising a self-aligned poly-metal stack formed over a semiconductor substrate where the interface between an oxidation barrier placed over the stack and an oxidized portion of the stack lies along the sidewall of the poly-metal stack. A semiconductor structure is also provided where an etch stop layer is present in the poly region of the poly-metal stack. The present invention also relates more broadly to a memory cell array and a computer system including the poly-metal stack of the present invention.Type: GrantFiled: April 18, 2005Date of Patent: March 24, 2009Assignee: Micron Technology, Inc.Inventor: Vishnu K. Agarwal
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Patent number: 7491602Abstract: Systems, devices, structures, and methods are described that inhibit atomic migration that creates an open contact between a metallization layer and a conductive layer of a semiconductor structure. A layer of an inhibiting substance may be used to inhibit a net flow of atoms so as to maintain conductivity between the metallization layer and the conductive layer of the semiconductor structure. Such layer of inhibiting substance acts even with the presence of point defects for a given temperature.Type: GrantFiled: July 8, 2003Date of Patent: February 17, 2009Assignee: Micron Technology, Inc.Inventor: Vishnu K. Agarwal
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Patent number: 7488665Abstract: Structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices are disclosed. The capacitors include monolithically-fabricated upright microstructures, i.e., those having large height/width (H/W) ratios, which are mechanical reinforcement against shear forces and the like, by a brace layer that transversely extends between lateral sides of at least two of the free-standing microstructures. The brace layer is formed as a microbridge type structure spanning between the upper ends of the two or more microstructures.Type: GrantFiled: October 27, 2004Date of Patent: February 10, 2009Assignee: Micron Technology, Inc.Inventors: Vishnu K. Agarwal, Gurtej Sandhu
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Patent number: 7446363Abstract: The invention comprises integrated circuitry and to methods of forming capacitors. In one implementation, integrated circuitry includes a capacitor having a first capacitor electrode, a second capacitor electrode and a high K capacitor dielectric region received therebetween. The high K capacitor dielectric region has a high K substantially amorphous material layer and a high K substantially crystalline material layer. In one implementation, a capacitor forming method includes forming a first capacitor electrode layer over a substrate. A substantially amorphous first high K capacitor dielectric material layer is deposited over the first capacitor electrode layer. The substantially amorphous high K first capacitor dielectric material layer is converted to be substantially crystalline. After the converting, a substantially amorphous second high K capacitor dielectric material layer is deposited over the substantially crystalline first high K capacitor dielectric material layer.Type: GrantFiled: February 24, 2006Date of Patent: November 4, 2008Assignee: Micron Technology, Inc.Inventor: Vishnu K. Agarwal
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Publication number: 20080226247Abstract: A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.Type: ApplicationFiled: March 13, 2008Publication date: September 18, 2008Inventors: Guy T. Blalock, Howard E. Rhodes, Vishnu K. Agarwal, Gurtej Singh Sandhu, James S. Foresi, Jean-Francois Viens, Dale G. Fried
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Patent number: 7390712Abstract: Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The enhanced capacitor includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second electrode having a compound. The compound includes a first substance and a second substance. The second electrode includes a trace amount of the first substance. The morphology of the semiconductor structure remains stable when the trace amount of the first substance is oxidized during crystallization of the dielectric. In one embodiment, the crystalline structure of the dielectric describes substantially a (001) lattice plane.Type: GrantFiled: April 30, 2007Date of Patent: June 24, 2008Assignee: Micron Technology, Inc.Inventors: Cem Basceri, Vishnu K. Agarwal, Dan Gealy
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Patent number: 7359607Abstract: A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.Type: GrantFiled: August 30, 2004Date of Patent: April 15, 2008Assignee: Micron Technology, Inc.Inventors: Guy T. Blalock, Howard E. Rhodes, Vishnu K. Agarwal, Gurtej Singh Sandhu, James S. Foresi, Jean-Francois Viens, Dale G. Fried
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Patent number: 7288808Abstract: A capacitor fabrication method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer. The method may further include forming rugged polysilicon over the substrate, the first electrode being over the rugged polysilicon. Accordingly, the outer surface area of the first electrode can be at least 30% greater than the outer surface area of the substrate without the first electrode including polysilicon.Type: GrantFiled: January 15, 2002Date of Patent: October 30, 2007Assignee: Micron Technology, Inc.Inventors: Vishnu K. Agarwal, Garry A. Mercaldi
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Patent number: 7282666Abstract: A material processing system and method is disclosed for processing materials such as amorphous silicon in an annealing processes and lithography processes on a silicon wafer, as well as ablation processes. A first laser generates periodic pulses of radiation along a beam path directed at the target material. Similarly, at least one additional laser generates periodic pulses. A beam aligner redirects the beam path of the at least one laser, such that the beam from the at least one additional laser is directed at the target along a path colinear with the first laser's beam path. As a result, all the lasers are directed at the target along the same combined beam path. The periodic pulses of the at least one additional laser are delayed relative to the first laser such that multiple pulses impinge on the target within a single pulse cycle of any given laser.Type: GrantFiled: May 7, 2004Date of Patent: October 16, 2007Assignee: Micron Technology, Inc.Inventors: Vishnu K. Agarwal, William A. Stanton
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Patent number: 7282756Abstract: Structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices are disclosed. The capacitors include monolithically-fabricated upright microstructures, i.e., those having large height/width (H/W) ratios, which are mechanical reinforcement against shear forces and the like, by a brace layer that transversely extends between lateral sides of at least two of the free-standing microstructures. The brace layer is formed as a microbridge type structure spanning between the upper ends of the two or more microstructures.Type: GrantFiled: September 22, 2003Date of Patent: October 16, 2007Assignee: Micron Technology Inc.Inventors: Vishnu K. Agarwal, Gurtej Sandhu