Abstract: CMOS image sensors have charge storage capacitors connected to various light sensitive and/or electrical elements. The capacity of the capacitors used for each pixel is tailored to the color to be detected. Charge storage capacitors may be formed entirely over a field oxide region of the CMOS imager, entirely over an active area of a pixel sensor cell, or partially over a field oxide region and partially over an active pixel area of a pixel sensor cell.

Abstract: A ferroelectric or high dielectric constant capacitor having a multilayer lower electrode comprising at least two layers—a platinum layer and a platinum-rhodium layer—for use in a random access memory (RAM) cell. The platinum layer of the lower electrode adjoins the capacitor dielectric, which is a ferroelectric or high dielectric constant dielectric such as BST, PZT, SBT or tantalum pentoxide. The platinum-rhodium layer serves as an oxidation barrier and may also act as an adhesion layer for preventing separation of the lower electrode from the substrate, thereby improving capacitor performance. The multilayer electrode may have titanium and/or titanium nitride layers under the platinum-rhodium layer for certain applications. The capacitor has an upper electrode which may be a conventional electrode or which may have a multilayer structure similar to that of the lower electrode. Processes for manufacturing the multilayer lower electrode and the capacitor are also disclosed.

Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.

Abstract: A method for forming a rough ruthenium-containing layer on the surface of a substrate assembly includes providing a ruthenium-containing precursor into the reaction chamber. A rough ruthenium layer may be deposited on the surface of the substrate assembly at a rate of about 100 ?/minute to about 500 ?/minute using the ruthenium-containing precursor. Further, a rough ruthenium oxide layer may be formed by providing a ruthenium-containing precursor and an oxygen-containing precursor into the reaction chamber to deposit the rough ruthenium oxide layer on the surface of the substrate assembly at a rate of about 100 ?/minute to about 1200 ?/minute. An anneal of the layers may be performed to further increase the roughness. In addition, conductive structures including a rough ruthenium layer or a rough ruthenium oxide layer are provided. Such layers may be used in conjunction with non-rough ruthenium and/or non-rough ruthenium oxide layers to form conductive structures.

Abstract: The invention includes methods of forming capacitors and capacitor constructions. In one implementation, a method of forming a capacitor includes forming a first capacitor electrode. A first layer of a first capacitor dielectric material is formed over the first capacitor electrode. A second layer of the first capacitor dielectric material is formed on the first layer. A second capacitor electrode is formed over the second layer of the first capacitor dielectric material. A capacitor in accordance with an implementation of the invention includes a pair of capacitor electrodes having capacitor dielectric material therebetween comprising a composite of two immediately juxtaposed and contacting, yet discrete, layers of the same capacitor dielectric material.

Abstract: Polishing pads used in the manufacturing of microelectronic devices, and apparatuses and methods for making and using such polishing pads. In one aspect of the invention, a polishing pad for planarizing microelectronic-device substrate assemblies has a backing member including a first surface and a second surface, a plurality of pattern elements distributed over the first surface of the backing member, and a hard cover layer over the pattern elements. The pattern elements define a plurality of contour surfaces projecting away from the first surface of the backing member. The cover layer at least substantially conforms to the contour surfaces of the pattern elements to form a plurality of hard nodules projecting away from the first surface of the backing member. The hard nodules define abrasive elements to contact and abrade material from a microelectronic-device substrate assembly. As such, the cover layer defines at least a portion of a planarizing surface of the polishing pad.

Abstract: An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug. In one embodiment, the intermediate plug is slightly shorter than an adjacent container-shaped capacitor. In another embodiment, the intermediate plug is about as high as an adjacent stud capacitor.

Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.

Abstract: In accordance with one embodiment of the present invention, a method of forming an etch stop layer in a semiconductor structure is provided. A polysilicon layer on the semiconductor substrate and ions are implanted into the polysilicon layer to form an etch stop layer. An oxide layer can be provided between the semiconductor substrate and the polysilicon layer.

Abstract: Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient.

Abstract: Integrated memory circuits, key components in thousands of electronic and computer products, have been made using ferroelectric materials, which offer faster write cycles and lower power requirements than some other materials. However, the present inventors have recognized, for example, that conventional techniques for working with the polymers produce polymer layers with thickness variations that compromise performance and manufacturing yield. Accordingly, the present inventors devised unique methods and structures for polymer-based ferroelectric memories. One exemplary method entails forming an insulative layer on a substrate, forming two or more first conductive structures, with at least two of the first conductive structures separated by a gap, forming a gap-filling structure within the gap, and forming a polymer-based ferroelectric layer over the gap-filling structure and the first conductive structures. In some embodiments, the gap-filling structure is a polymer, a spin-on-glass, or a flow-fill oxide.

Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.

Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.

Abstract: A ferroelectric or high dielectric constant capacitor having a multilayer lower electrode comprising at least two layers—a platinum layer and a platinum-rhodium layer—for use in a random access memory (RAM) cell. The platinum layer of the lower electrode adjoins the capacitor dielectric, which is a ferroelectric or high dielectric constant dielectric such as BST, PZT, SBT or tantalum pentoxide. The platinum-rhodium layer serves as an oxidation barrier and may also act as an adhesion layer for preventing separation of the lower electrode from the substrate, thereby improving capacitor performance. The multilayer electrode may have titanium and/or titanium nitride layers under the platinum-rhodium layer for certain applications. The capacitor has an upper electrode which may be a conventional electrode or which may have a multilayer structure similar to that of the lower electrode. Processes for manufacturing the multilayer lower electrode and the capacitor are also disclosed.

Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.

Abstract: A method for forming a rough ruthenium-containing layer on the surface of a substrate assembly includes providing a ruthenium-containing precursor into the reaction chamber. A rough ruthenium layer may be deposited on the surface of the substrate assembly at a rate of about 100 Å/minute to about 500 Å/minute using the ruthenium-containing precursor. Further, a rough ruthenium oxide layer may be formed by providing a ruthenium-containing precursor and an oxygen-containing precursor into the reaction chamber to deposit the rough ruthenium oxide layer on the surface of the substrate assembly at a rate of about 100 Å/minute to about 1200 Å/minute. An anneal of the layers may be performed to further increase the roughness. In addition, conductive structures including a rough ruthenium layer or a rough ruthenium oxide layer are provided. Such layers may be used in conjunction with non-rough ruthenium and/or non-rough ruthenium oxide layers to form conductive structures.

Abstract: A planarizing pad for planarizing a microelectronic substrate, and a method and apparatus for forming the planarizing pad. In one embodiment, planarizing pad material is mixed with compressed gas to form a plurality of discrete elements that are distributed on a support material. At least a portion of the discrete elements are spaced apart from each other on the support material to form a textured surface for engaging a microelectronic substrate and removing material from the microelectronic substrate. The discrete elements can be uniformly or randomly distributed on the support material, and the discrete elements can be directly affixed to the support material or affixed to the support material with an adhesive.

Abstract: Container structures for use in integrated circuits and methods of their manufacture. The container structures include a bottom conductive layer, a top conductive layer and a dielectric layer interposed between the bottom conductive layer and the top conductive layer. The container structures further include a diffusion barrier layer interposed between the dielectric layer and the bottom conductive layer. The diffusion barrier layer acts to inhibit atomic diffusion to at least a portion of the bottom conductive layer, particularly atomic diffusion of oxygen during formation or annealing of the dielectric layer. The container structures are especially adapted for use as container capacitors. The container capacitors are further adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: In one aspect, the invention encompasses a semiconductor circuit construction including a material which comprises Q, R, S and B. In such construction, Q comprises one or more refractory metals, R is selected from the group consisting of one or more of tungsten, aluminum and silicon, S is selected from the group consisting of one or more of nitrogen and oxygen, and B is boron. Also, in such construction R and Q do not comprise a common element. In another aspect, the invention encompasses a method of forming a capacitor. A first capacitor electrode is formed, a diffusion barrier layer is formed proximate the first capacitor electrode, and a dielectric layer is formed to be separated from the first capacitor electrode by the diffusion barrier layer. A second capacitor electrode is formed to be separated from the first electrode by the dielectric layer.

Abstract: A ferroelectric or high dielectric constant capacitor having a multilayer lower electrode comprising at least two layers—a platinum layer and a platinum-rhodium layer—for use in a random access memory (RAM) cell. The platinum layer of the lower electrode adjoins the capacitor dielectric, which is a ferroelectric or high dielectric constant dielectric such as BST, PZT, SBT or tantalum pentoxide. The platinum-rhodium layer serves as an oxidation barrier and may also act as an adhesion layer for preventing separation of the lower electrode from the substrate, thereby improving capacitor performance. The multilayer electrode may have titanium and/or titanium nitride layers under the platinum-rhodium layer for certain applications. The capacitor has an upper electrode which may be a conventional electrode or which may have a multilayer structure similar to that of the lower electrode. Processes for manufacturing the multilayer lower electrode and the capacitor are also disclosed.