Abstract: A method and apparatus for endpointing a planarization process of a microelectronic substrate. In one embodiment, the apparatus may include a species analyzer that receives a slurry resulting from the planarization process and analyzes the slurry to determine the presence of an endpointing material implanted beneath the surface of the microelectronic substrate. The species analyzer may include a mass spectrometer or a spectrum analyzer. In another embodiment, the apparatus may include a radiation source that directs impinging radiation toward the microelectronic substrate, exciting atoms of the substrate, which in turn produce an emitted radiation. A radiation detector is positioned proximate to the substrate to receive the emitted radiation and determine the endpoint by determining the intensity of the radiation emitted by the endpointing material.

Abstract: A planarizing pad for planarizing a microelectronic substrate, and a method and apparatus for forming the planarizing pad. In one embodiment, planarizing pad material is mixed with compressed gas to form a plurality of discrete elements that are distributed on a support material. At least a portion of the discrete elements are spaced apart from each other on the support material to form a textured surface for engaging a microelectronic substrate and removing material from the microelectronic substrate. The discrete elements can be uniformly or randomly distributed on the support material, and the discrete elements can be directly affixed to the support material or affixed to the support material with an adhesive.

Abstract: CMOS image sensors have charge storage capacitors connected to various light sensitive and/or electrical elements. The capacity of the capacitors used for each pixel is tailored to the color to be detected. Charge storage capacitors may be formed entirely over a filed oxide region of the CMOS imager, entirely over an active area of a pixel sensor cell, or partially over a field oxide region and partially over an active pixel area of a pixel sensor cell.

Abstract: In one aspect, the invention includes a method of forming a material comprising tungsten and nitrogen, comprising: a) providing a substrate; b) depositing a layer comprising tungsten and nitrogen over the substrate; and c) in a separate step from the depositing, exposing the layer comprising tungsten and nitrogen to a nitrogen-containing plasma. In another aspect, the invention includes a method of forming a capacitor, comprising: a) forming a first electrical node; b) forming a dielectric layer over the first electrical node; c) forming a second electrical node; and d) providing a layer comprising tungsten and nitrogen between the dielectric layer and one of the electrical nodes, the providing comprising; i) depositing a layer comprising tungsten and nitrogen; and ii) in a separate step from the depositing, exposing the layer comprising tungsten and nitrogen to a nitrogen-containing plasma.

Abstract: A conductive composition of tantalum nitride is disclosed for use as a conductive element in integrated circuits. The layer is shown employed in a memory cell, and in particular in a cell incorporating a high dielectric constant material such as Ta2O5. The tantalum nitride can serve as a barrier layer protecting an underlying contact plug, or can serve as the top or bottom electrode of the memory cell capacitor. The tantalum nitride has a nitrogen content of between about 7% and 40%, thereby balancing susceptibility to oxidation with conductivity. In an illustrative embodiment, the tantalum nitride layer is a bilayer formed of a thick portion having a low nitrogen concentration, and thin portion with a higher nitrogen concentration. The thick portion thus carries the bulk of the current with low resistivity, while the thinner portion is highly resistant to oxidation.

Abstract: A ferroelectric or high dielectric constant capacitor having a multilayer lower electrode comprising at least two layers—a platinum layer and a platinum-rhodium layer—for use in a random access memory (RAM) cell is disclosed. The platinum layer of the lower electrode is formed such that it adjoins the capacitor dielectric, which is a ferroelectric or high dielectric constant dielectric such as BST, PZT, SBT or tantalum pentoxide. The platinum-rhodium layer serves as an oxidation barrier and may also act as an adhesion layer for preventing separation of the lower electrode from the substrate, thereby improving capacitor performance. The multilayer electrode may have titanium and/or titanium nitride layers under the platinum-rhodium layer for certain applications. The capacitor has an upper electrode which may be a conventional electrode or which may have a multilayer structure similar to that of the lower electrode.

Abstract: The present invention provides a method and apparatus for producing 0 degree light and 180 degree phase shifted light having substantially equal intensities as both lights exit an alternating phase shift reticle. A material is inserted within the etched portion of the 180 degree phase shift channel of a reticle, wherein the material contains an index of refraction such that the first order light (+1, −1) is propagated through the 180 degree channel. The end result is a 180 degree phase shifted light having an intensity substantially equal to that of the 0 degree light.

Abstract: An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug. In one embodiment, the intermediate plug is slightly shorter than an adjacent container-shaped capacitor. In another embodiment, the intermediate plug is about as high as an adjacent stud capacitor.

Abstract: A ferroelectric or high dielectric constant capacitor having a multilayer lower electrode comprising at least two layers—a platinum layer and a platinum-rhodium layer—for use in a random access memory (RAM) cell. The platinum layer of the lower electrode adjoins the capacitor dielectric, which is a ferroelectric or high dielectric constant dielectric such as BST, PZT, SBT or tantalum pentoxide. The platinum-rhodium layer serves as an oxidation barrier and may also act as an adhesion layer for preventing separation of the lower electrode from the substrate, thereby improving capacitor performance. The multilayer electrode may have titanium and/or titanium nitride layers under the platinum-rhodium layer for certain applications. The capacitor has an upper electrode which may be a conventional electrode or which may have a multilayer structure similar to that of the lower electrode. Processes for manufacturing the multilayer lower electrode and the capacitor are also disclosed.

Abstract: CMOS image sensors have charge storage capacitors connected to various light sensitive and/or electrical elements. The capacity of the capacitors used for each pixel is tailored to the color to be detected. Charge storage capacitors may be formed entirely over a field oxide region of the CMOS imager, entirely over an active area of a pixel sensor cell, or partially over a field oxide region and partially over an active pixel area of a pixel sensor cell.

Abstract: Systems, devices, structures, and methods are described that inhibit atomic migration that creates an open contact between a metallization layer and a conductive layer of a semiconductor structure. A layer of an inhibiting substance may be used to inhibit a net flow of atoms so as to maintain conductivity between the metallization layer and the conductive layer of the semiconductor structure. Such layer of inhibiting substance acts even with the presence of point defects for a given temperature.

Abstract: A planarizing pad for planarizing a microelectronic substrate, and a method and apparatus for forming the planarizing pad. In one embodiment, planarizing pad material is mixed with compressed gas to form a plurality of discrete elements that are distributed on a support material. At least a portion of the discrete elements are spaced apart from each other on the support material to form a textured surface for engaging a microelectronic substrate and removing material from the microelectronic substrate. The discrete elements can be uniformly or randomly distributed on the support material, and the discrete elements can be directly affixed to the support material or affixed to the support material with an adhesive.

Abstract: Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxynitride barrier layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxynitride barrier layer acts to reduce undesirable oxidation of its associated electrode. Each metal oxynitride barrier layer can further aid in the repairing of oxygen vacancies in a metal oxide dielectric. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: The invention includes methods of forming capacitors and capacitor constructions. In one implementation, a method of forming a capacitor includes forming a first capacitor electrode. A first layer of a first capacitor dielectric material is formed over the first capacitor electrode. A second layer of the first capacitor dielectric material is formed on the first layer. A second capacitor electrode is formed over the second layer of the first capacitor dielectric material. A capacitor in accordance with an implementation of the invention includes a pair of capacitor electrodes having capacitor dielectric material therebetween comprising a composite of two immediately juxtaposed and contacting, yet discrete, layers of the same capacitor dielectric material.

Abstract: A diffusion barrier layer comprising TiNxBy is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a TDMAT process including boron. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a CVD process. The diffusion barrier layer is of particular utility in conjunction with tungsten or tungsten silicide conductive layers formed by CVD.

Abstract: A diffusion barrier layer comprising TiNxBy is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a TDMAT process including boron. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a CVD process. The diffusion barrier layer is of particular utility in conjunction with tungsten or tungsten silicide conductive layers formed by CVD.

Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.

Abstract: Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxynitride barrier layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxynitride barrier layer acts to reduce undesirable oxidation of its associated electrode. Each metal oxynitride barrier layer can further aid in the repairing of oxygen vacancies in a metal oxide dielectric. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.

Abstract: An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug. In one embodiment, the intermediate plug is slightly shorter than an adjacent container-shaped capacitor. In another embodiment, the intermediate plug is about as high as an adjacent stud capacitor.