Patents by Inventor Vishnu K. Khemka
Vishnu K. Khemka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10672902Abstract: A field effect device includes a semiconductor body separating a source and a drain, both source and drain coupled to the semiconductor body. An insulated control gate is located over the semiconductor body between the source and drain and configured to control a conductive channel extending between the source and drain. First and second doped regions such as highly-doped regions are adjacent to the source. The first or second doped region may be a cathode short region electrically coupled to the source. The cathode short region may be used in a bidirectional power MOSFET.Type: GrantFiled: April 8, 2019Date of Patent: June 2, 2020Assignee: NXP USA, Inc.Inventors: Tanuj Saxena, Vishnu K. Khemka, Raghu Gupta, Moaniss Zitouni, Ganming Qin
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Publication number: 20190237571Abstract: A field effect device includes a semiconductor body separating a source and a drain, both source and drain coupled to the semiconductor body. An insulated control gate is located over the semiconductor body between the source and drain and configured to control a conductive channel extending between the source and drain. First and second doped regions such as highly-doped regions are adjacent to the source. The first or second doped region may be a cathode short region electrically coupled to the source. The cathode short region may be used in a bidirectional power MOSFET.Type: ApplicationFiled: April 8, 2019Publication date: August 1, 2019Inventors: Tanuj Saxena, Vishnu K. Khemka, Raghu Gupta, Moaniss Zitouni, Ganming Qin
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Patent number: 10297684Abstract: A field effect device includes a semiconductor body separating a source and a drain, both source and drain coupled to the semiconductor body. An insulated control gate is located over the semiconductor body between the source and drain and configured to control a conductive channel extending between the source and drain. First and second doped regions such as highly-doped regions are adjacent to the source. The first or second doped region may be a cathode short region electrically coupled to the source. The cathode short region may be used in a bidirectional power MOSFET.Type: GrantFiled: September 29, 2017Date of Patent: May 21, 2019Assignee: NXP USA, Inc.Inventors: Tanuj Saxena, Vishnu K. Khemka, Raghu Gupta, Moaniss Zitouni, Ganming Qin
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Publication number: 20190103484Abstract: A field effect device includes a semiconductor body separating a source and a drain, both source and drain coupled to the semiconductor body. An insulated control gate is located over the semiconductor body between the source and drain and configured to control a conductive channel extending between the source and drain. First and second doped regions such as highly-doped regions are adjacent to the source. The first or second doped region may be a cathode short region electrically coupled to the source. The cathode short region may be used in a bidirectional power MOSFET.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Tanuj Saxena, Vishnu K. Khemka, Raghu Gupta, Moaniss Zitouni, Ganming Qin
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Patent number: 9209277Abstract: Fabrication processes for semiconductor devices are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type.Type: GrantFiled: January 23, 2013Date of Patent: December 8, 2015Assignee: FREESCALE SEMICONDUCTOR INC.Inventors: Tahir A. Khan, Bernhard H. Grote, Vishnu K. Khemka, Ronghua Zhu
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Patent number: 8907419Abstract: A laterally double diffused metal oxide semiconductor device includes a well region having a first conductivity, a first carrier redistribution region having the first conductivity type, wherein the second well region is under the well region, and a highly doped buried layer under the second well region. The highly doped buried layer has the first conductivity type and has a dopant concentration less than that of the well region and less than that of the first carrier redistribution region, and the buried layer is tied to the first well region. In addition, a method for forming the laterally double diffused metal oxide semiconductor device, which may use epitaxial growth, is disclosed.Type: GrantFiled: September 13, 2012Date of Patent: December 9, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Tahir A. Khan, Vishnu K. Khemka, Ronghua Zhu
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Patent number: 8816434Abstract: An LDMOS transistor includes a substrate of semiconductor material, an insulator layer overlying the substrate, a semiconductor layer overlying the insulator layer, a RESURF region, and a gate. The semiconductor layer includes a first conductivity type well region, a second conductivity type source region in contact with the first conductivity type well region, a second conductivity type drain region. The RESURF region includes at least one first conductivity type material portion, and at least one portion of the at least one first conductivity type material portion electrically coupled to the first conductivity type well region. A semiconductor material having a second conductivity type is located below the RESURF region. The second conductivity type semiconductor material is also located over a part of the RESURF region. The gate is located over the first conductivity type well region and over the RESURF region.Type: GrantFiled: December 19, 2013Date of Patent: August 26, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Bernhard H. Grote, Tahir A. Khan, Vishnu K. Khemka, Ronghua Zhu
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Publication number: 20140103431Abstract: An LDMOS transistor includes a substrate of semiconductor material, an insulator layer overlying the substrate, a semiconductor layer overlying the insulator layer, a RESURF region, and a gate. The semiconductor layer includes a first conductivity type well region, a second conductivity type source region in contact with the first conductivity type well region, a second conductivity type drain region. The RESURF region includes at least one first conductivity type material portion, and at least one portion of the at least one first conductivity type material portion electrically coupled to the first conductivity type well region. A semiconductor material having a second conductivity type is located below the RESURF region. The second conductivity type semiconductor material is also located over a part of the RESURF region. The gate is located over the first conductivity type well region and over the RESURF region.Type: ApplicationFiled: December 19, 2013Publication date: April 17, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: BERNHARD H. GROTE, TAHIR A. KHAN, VISHNU K. KHEMKA, RONGHUA ZHU
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Patent number: 8623732Abstract: An LDMOS transistor includes a substrate of semiconductor material, an insulator layer overlying the substrate, a semiconductor layer overlying the insulator layer, a RESURF region, and a gate. The semiconductor layer includes a first conductivity type well region, a second conductivity type source region in contact with the first conductivity type well region, a second conductivity type drain region. The RESURF region includes at least one first conductivity type material portion, and at least one portion of the at least one first conductivity type material portion electrically coupled to the first conductivity type well region. A semiconductor material having a second conductivity type is located below the RESURF region. The second conductivity type semiconductor material is also located over a part of the RESURF region. The gate is located over the first conductivity type well region and over the RESURF region.Type: GrantFiled: June 17, 2010Date of Patent: January 7, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Bernhard H. Grote, Tahir A. Khan, Vishnu K. Khemka, Ronghua Zhu
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Patent number: 8384184Abstract: A semiconductor device and a related fabrication process are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type.Type: GrantFiled: September 15, 2010Date of Patent: February 26, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Tahir A. Khan, Bernhard H. Grote, Vishnu K. Khemka, Ronghua Zhu
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Publication number: 20130009243Abstract: A laterally double diffused metal oxide semiconductor device includes a well region having a first conductivity, a first carrier redistribution region having the first conductivity type, wherein the second well region is under the well region, and a highly doped buried layer under the second well region. The highly doped buried layer has the first conductivity type and has a dopant concentration less than that of the well region and less than that of the first carrier redistribution region, and the buried layer is tied to the first well region. In addition, a method for forming the laterally double diffused metal oxide semiconductor device, which may use epitaxial growth, is disclosed.Type: ApplicationFiled: September 13, 2012Publication date: January 10, 2013Applicant: Freescale Semiconductor, Inc.Inventors: Tahir A. Khan, Vishnu K. Khemka, Ronghua Zhu
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Patent number: 8344472Abstract: Transistors (21, 41) employing floating buried layers may be susceptible to noise coupling into the floating buried layers. In IGFETS this is reduced or eliminated by providing a normally-ON switch (80, 80?) coupling the buried layer (102, 142, 172, 202) and the IGFET source (22, 42) or drain (24, 44). When the transistor (71, 91) is OFF, this clamps the buried layer voltage and substantially prevents noise coupling thereto. When the drain-source voltage VDS exceeds the switch's (80, 80?) threshold voltage Vt, it turns OFF, allowing the buried layer (102, 142, 172, 202) to float, and thereby resume normal transistor action without degrading the breakdown voltage or ON-resistance. In a preferred embodiment, a normally-ON lateral JFET (801, 801?, 801-1, 801-2, 801-3) conveniently provides this switching function.Type: GrantFiled: March 30, 2010Date of Patent: January 1, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Vishnu K. Khemka, Tahir A. Khan, Weixiao Huang, Ronghua Zhu
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Patent number: 8338872Abstract: Transistors (21, 41) employing floating buried layers (BL) (72) may exhibit transient breakdown voltage (BVdss)TR significantly less than (BVdss)DC. It is found that this occurs because the floating BL (72) fails to rapidly follow the applied transient, causing the local electric field within the device to temporarily exceed avalanche conditions. (BVdss)TR of such transistors (69. 69?) can be improved to equal or exceed (BVdss)DC by including a charge pump capacitance (94, 94?) coupling the floating BL (72) to whichever high-side terminal (28, 47) receives the transient. The charge pump capacitance (94, 94?) may be external to the transistor (69, 69?), may be formed on the device surface (71) or, may be formed internally to the transistor (69-3, 69?-3) using a dielectric deep trench isolation wall (100) separating DC isolated sinker regions (86, 88) extending to the BL (72). The improvement is particularly useful for LDMOS devices.Type: GrantFiled: March 30, 2010Date of Patent: December 25, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Vishnu K. Khemka, Tahir A. Khan, Ronghua Zhu, Weixiao Huang, Bernhard H. Grote
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Patent number: 8330220Abstract: A laterally double diffused metal oxide semiconductor device includes a well region having a first conductivity, a first carrier redistribution region having the first conductivity type, wherein the second well region is under the well region, and a highly doped buried layer under the second well region. The highly doped buried layer has the first conductivity type and has a dopant concentration less than that of the well region and less than that of the first carrier redistribution region, and the buried layer is tied to the first well region. In addition, a method for forming the laterally double diffused metal oxide semiconductor device, which may use epitaxial growth, is disclosed.Type: GrantFiled: April 29, 2010Date of Patent: December 11, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Tahir A. Khan, Vishnu K. Khemka, Ronghua Zhu
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Patent number: 8278710Abstract: An LDMOSFET transistor (100) is provided which includes a substrate (101), an epitaxial drift region (104) in which a drain region (116) is formed, a first well region (107) in which a source region (112) is formed, a gate electrode (120) formed adjacent to the source region (112) to define a first channel region (14), and a grounded substrate injection suppression guard structure that includes a patterned buried layer (102) in ohmic contact with an isolation well region (103) formed in a predetermined upper region of the substrate so as to be spaced apart from the first well region (107) and from the drain region (116), where the buried layer (102) is disposed below the first well region (107) but not below the drain region (116).Type: GrantFiled: July 23, 2010Date of Patent: October 2, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Vishnu K. Khemka, Stephen J. Cosentino, Tahir A. Khan, Adolfo C. Reyes, Ronghua Zhu
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Patent number: 8193585Abstract: Methods and apparatus are provided for fabricating a semiconductor device structure. The semiconductor device structure comprises a buried region having a first conductivity type, a first region having a second conductivity type overlying the buried region, a source region having the first conductivity type overlying the first region, and a drain region having the first conductivity type overlying the first region. The semiconductor device structure further comprises a second region having the first conductivity type overlying the buried region, the second region abutting the buried region to form an electrical contact with the buried region, and a first resistance configured electrically in series with the second region and the buried region. The combined series resistance of the first resistance and the second region is greater than a resistance of the buried region.Type: GrantFiled: October 29, 2009Date of Patent: June 5, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Bernhard H. Grote, Vishnu K. Khemka, Tahir A. Khan, Weixiao Huang, Ronghua Zhu
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Patent number: 8188543Abstract: An electronic device can include a substrate, a buried insulating layer overlying the substrate, and a semiconductor layer overlying the buried insulating layer, wherein the semiconductor layer is substantially monocrystalline. The electronic device can also include a conductive structure extending through the semiconductor layer and buried insulating layer and abutting the substrate, and an insulating spacer lying between the conductive structure and each of the semiconductor layer and the buried insulating layer.Type: GrantFiled: November 3, 2006Date of Patent: May 29, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Todd C. Roggenbauer, Vishnu K. Khemka, Ronghua Zhu, Amitava Bose, Paul Hui, Xiaoqiu Huang
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Publication number: 20120061758Abstract: A semiconductor device and a related fabrication process are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type.Type: ApplicationFiled: September 15, 2010Publication date: March 15, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Tahir A. Khan, Bernhard H. Grote, Vishnu K. Khemka, Ronghua Zhu
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Patent number: 8134222Abstract: Methods and apparatus are described for MOS capacitors (MOS CAPs). The apparatus comprises a substrate having Ohmically coupled N and P semiconductor regions covered by a dielectric. A conductive electrode overlies the dielectric above these N and P regions. Use of the Ohmically coupled N and P regions substantially reduces the variation of capacitance with applied voltage associated with ordinary MOS CAPs. When these N and P regions have unequal doping, the capacitance variation may still be substantially compensated by adjusting the properties of the dielectric above the N and P regions and/or relative areas of the N and P regions or both. Accordingly, such MOS CAPS may be more easily integrated with other semiconductor devices with minimal or no disturbance to the established integrated circuit (IC) manufacturing process and without significantly increasing the occupied area beyond that required for a conventional MOS CAP.Type: GrantFiled: October 12, 2010Date of Patent: March 13, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Tahir A. Khan, Amitava Bose, Vishnu K. Khemka, Ronghua Zhu
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Publication number: 20120018804Abstract: An LDMOSFET transistor (100) is provided which includes a substrate (101), an epitaxial drift region (104) in which a drain region (116) is formed, a first well region (107) in which a source region (112) is formed, a gate electrode (120) formed adjacent to the source region (112) to define a first channel region (14), and a grounded substrate injection suppression guard structure that includes a patterned buried layer (102) in ohmic contact with an isolation well region (103) formed in a predetermined upper region of the substrate so as to be spaced apart from the first well region (107) and from the drain region (116), where the buried layer (102) is disposed below the first well region (107) but not below the drain region (116).Type: ApplicationFiled: July 23, 2010Publication date: January 26, 2012Inventors: Vishnu K. Khemka, Stephen J. Cosentino, Tahir A. Khan, Adolfo C. Reyes, Ronghua Zhu