Abstract: Apparatus and methods are provided for fabricating semiconductor devices with reduced bipolar effects. One apparatus includes a semiconductor body (120) including a surface and a transistor source (300) located in the semiconductor body proximate the surface, and the transistor source includes an area (310) of alternating conductivity regions (3110, 3120). Another apparatus includes a semiconductor body (120) including a first conductivity and a transistor source (500) located in the semiconductor body. The transistor source includes multiple regions (5120) including a second conductivity, wherein the regions and the semiconductor body form an area (510) of alternating regions of the first and second conductivities. One method includes implanting a semiconductor well (120) including a first conductivity in a substrate (110) and implanting a plurality of doped regions (5120) comprising a second conductivity in the semiconductor well.

Abstract: Methods and apparatus are provided for reducing substrate leakage current of RESURF LDMOSFET devices.

Abstract: A semiconductor device 10 is provided. A first layer 12 has a first dopant type; a second layer 14 is provided over the first layer 12; and a third layer 16 is provided over the second layer and has the first dopant type. A plurality of first and second semiconductor regions 22, 24 are within the third layer. The first semiconductor region 22 has the first dopant type, and the second semiconductor region 24 has the second dopant type. The first and second semiconductor regions 22, 24 are disposed laterally to one another in an alternating pattern to form a super junction, and the super junction terminates with a final second semiconductor region 24, 24? of the second dopant type.

Abstract: A improved MOSFET (50, 51, 75, 215) has a source (60) and drain (62) in a semiconductor body (56), surmounted by an insulated control gate (66) located over the body (56) between the source (60) and drain (62) and adapted to control a conductive channel (55) extending between the source (60) and drain (62). The insulated gate (66) is perforated by a series of openings (61) through which highly doped regions (69) in the form of a series of (e.g., square) dots (69) of the same conductivity type as the body (56) are provided, located in the channel (55), spaced apart from each other and from the source (60) and drain (62). These channel dots (69) are desirably electrically coupled to a highly doped contact (64) to the body (56). The resulting device (50, 51, 75, 215) has a greater SOA, higher breakdown voltage and higher HBM stress resistance than equivalent prior art devices (20) without the dotted channel. Threshold voltage is not affected.

Abstract: A low leakage bipolar Schottky diode (20, 40, 87) is formed by parallel lightly doped N (32, 52, 103) and P (22, 42, 100) regions adapted to form superjunction regions. First ends of the P regions (22, 42, 100) are terminated by P+ layers (21, 41, 121) and second, opposed ends of the N regions (32, 52, 103) are terminated by N+ layers (31, 51, 131). Silicide layers (24, 34, 44, 54, 134, 124) are provided in contact with both ends of the parallel N and P regions (22, 32, 42, 52, 100, 103), thereby forming at the first end ohmic contacts (28, 48) with the P+ regions (21, 41, 121) and Schottky contacts (37, 57) with the N regions 32, 52, 103) and at the second, opposite end, ohmic contacts (38, 58) with the N+ regions (31, 51, 131) and Schottky contacts (27, 47) with the P regions (22, 42, 100). When forward biased current flows in both N (32, 52) and P (22, 42) regions thereby reducing the forward drop.

Abstract: A improved MOSFET (50, 51, 75, 215) has a source (60) and drain (62) in a semiconductor body (56), surmounted by an insulated control gate (66) located over the body (56) between the source (60) and drain (62) and adapted to control a conductive channel (55) extending between the source (60) and drain (62). The insulated gate (66) is perforated by a series of openings (61) through which highly doped regions (69) in the form of a series of (e.g., square) dots (69) of the same conductivity type as the body (56) are provided, located in the channel (55), spaced apart from each other and from the source (60) and drain (62). These channel dots (69) are desirably electrically coupled to a highly doped contact (64) to the body (56). The resulting device (50, 51, 75, 215) has a greater SOA, higher breakdown voltage and higher HBM stress resistance than equivalent prior art devices (20) without the dotted channel. Threshold voltage is not affected.

Abstract: A process of forming an electronic device can include providing a semiconductor-on-insulator substrate including a substrate, a first semiconductor layer, and a buried insulating layer lying between the first semiconductor layer and the substrate. The process can also include forming a field isolation region within the semiconductor layer, and forming an opening extending through the semiconductor layer and the buried insulating layer to expose the substrate. The process can further include forming a conductive structure within the opening, wherein the conductive structure abuts the substrate.

Abstract: An electronic device can include a substrate, a buried insulating layer overlying the substrate, and a semiconductor layer overlying the buried insulating layer, wherein the semiconductor layer is substantially monocrystalline. The electronic device can also include a conductive structure extending through the semiconductor layer and buried insulating layer and abutting the substrate, and an insulating spacer lying between the conductive structure and each of the semiconductor layer and the buried insulating layer.

Abstract: Methods and apparatus are provided for semiconductor device (60, 95, 100, 106). The semiconductor device (60, 95, 100, 106), comprises a first region (64, 70) of a first conductivity type extending to a first surface (80), a second region (66) of a second, opposite, conductivity type forming with the first region (70) a first PN junction (65) extending to the first surface (80), a contact region (68) of the second conductivity type in the second region (66) at the first surface (80) and spaced apart from the first PN junction (65) by a first distance (LDS), and a third region (82, 96-98, 108) of the first conductivity type and of a second length (LBR), underlying the second region (66) and forming a second PN junction (63) therewith spaced apart from the first surface (80) and located closer to the first PN junction (65) than to the contact region (68). The breakdown voltage is enhanced without degrading other useful properties of the device (60, 95, 100, 106).

Abstract: A conductive layer includes a first portion that forms a Schottky region with an underlying first region having a first conductivity type. A second region of a second conductivity type underlies the first region, where the second conductivity type is opposite the first conductivity type. A third region of the first conductivity type immediately underlies the second region and is electrically coupled to a cathode of the device.

Abstract: A semiconductor device 10 is provided. A first layer 12 has a first dopant type; a second layer 14 is provided over the first layer 12; and a third layer 16 is provided over the second layer and has the first dopant type. A plurality of first and second semiconductor regions 22, 24 are within the third layer. The first semiconductor region 22 has the first dopant type, and the second semiconductor region 24 has the second dopant type. The first and second semiconductor regions 22, 24 are disposed laterally to one another in an alternating pattern to form a super junction, and the super junction terminates with a final second semiconductor region 24, 24? of the second dopant type.

Abstract: A semiconductor component and method of manufacture, including an insulated gate bipolar transistor (IGBT) (100, 200) that includes a semiconductor substrate (110) having a first conductivity type and buried semiconductor region (115) having a second conductivity type located above the semiconductor substrate. The IGBT further includes a first semiconductor region (120) having the first conductivity type located above the buried semiconductor region, a second semiconductor region (130) having the second conductivity type located above at least a portion of the first semiconductor region, an emitter (150) having the second conductivity type disposed in the second semiconductor region, and a collector (170) having the second conductivity type disposed in the first semiconductor region. A sinker region (140) is provided to electrically tie the buried semiconductor region (115) to the second semiconductor region (130).

Abstract: A Schottky device having a plurality of unit cells, each having a Schottky contact portion, surrounded by a termination structure that causes depletion regions to form in a vertical and horizontal direction, relative to a surface of the device, during a reverse bias voltage condition.

Abstract: A semiconductor component and method of manufacture, including an insulated gate bipolar transistor (IGBT) (100, 200, 300, 400) that includes a semiconductor substrate (110, 210, 310, 410) having a first conductivity type and buried semiconductor region (115, 215, 315, 415) having a second conductivity type located above the semiconductor substrate. The IGBT further includes a first semiconductor region (120, 220, 320, 420) having the first conductivity type located above the buried semiconductor region, a second semiconductor region (130, 230, 330, 430) having the first conductivity type located above the first semiconductor region, a third semiconductor region (140, 240, 340, 440) having the second conductivity type located above the first semiconductor region, an emitter (150, 250, 350, 450) having the first conductivity type disposed in the third semiconductor region, and a collector (170, 270, 370, 470) having the first conductivity type disposed in the third semiconductor region.

Abstract: A semiconductor component and method of manufacture, including an insulated gate bipolar transistor (IGBT) (100) including a semiconductor substrate (110) having a first conductivity type and buried semiconductor region (115) having a second conductivity type located above the semiconductor substrate. The IGBT further includes a plurality of first semiconductor regions (120) having the first conductivity type, a plurality of second semiconductor regions (130) having the first conductivity type, and a plurality of third semiconductor regions (140) having the second conductivity type. A sinker region (142) having the second conductivity type is disposed in a third semiconductor region and a first semiconductor region during manufacture to define the plurality of regions and tie the buried semiconductor region to the plurality of third semiconductor regions.

Abstract: An LDMOS transistor has a Schottky diode inserted at the center of a doped region of the LDMOS transistor. A Typical LDMOS transistor has a drift region in the center. In this case a Schottky diode is inserted at the center of this drift region which has the effect of providing a Schottky diode connected from source to drain in the forward direction so that the drain voltage is clamped to a voltage that is lower than the PN junction threshold, thereby avoiding forward biasing the PN junction. An alternative is to insert the Schottky diode at the well in which the source is formed, which is on the periphery of the LDMOS transistor. In such case the Schottky diode is formed differently but still is connected from source to drain in the forward direction to achieve the desired voltage clamping at the drain.

Abstract: In one embodiment, semiconductor device 10 comprises a diode which uses isolation regions (34, 16, and 13) and a plurality of dopant concentrations (30, 20, 24, and 26) which may be used to limit the parasitic current that is injected into the semiconductor substrate (12). Various biases on the isolation regions (34, 16, and 13) may be used to affect the behavior of semiconductor device (10). In addition, a conductive layer (28) may be formed overlying the junction between anode (42) and cathode (40). This conductive layer (28) may decrease the electric field in selected regions in order to increase the maximum voltage that may be applied to cathode (40).

Abstract: A regular Schottky diode or a device that has a Schottky diode characteristic and an MOS transistor are coupled in series to provide a significant improvement in leakage current and breakdown voltage with only a small degradation in forward current. In the reverse bias case, there is a small reverse bias current but the voltage across the Schottky diode remains small due the MOS transistor. Nearly all of the reverse bias voltage is across the MOS transistor until the MOS transistor breaks down. This transistor breakdown, however, is not initially destructive because the Schottky diode limits the current. As the reverse bias voltage continues to increase the Schottky diodes begins to absorb more of the voltage. This increases the leakage current but the breakdown voltage is a somewhat additive between the transistor and the Schottky diode.

Abstract: A semiconductor component includes a semiconductor substrate (110) having first and second portions (111, 112) with a first conductivity type, a transistor (120) at least partially located in the semiconductor substrate, and a switching circuit (150, 350, 650, 850). The transistor includes (i) a first doped region in the first portion of the semiconductor substrate and having the first conductivity type (ii) a terminal, which includes a second doped region having a second conductivity type and located in the first portion of the semiconductor substrate and over the first doped region, and (iii) a third doped region having the second conductivity type and located in the semiconductor substrate below the first portion of the semiconductor substrate and above the second portion of the semiconductor substrate. The switching circuit is electrically coupled to the third doped region to adjust the bias of the third doped region.

Abstract: A semiconductor component includes a semiconductor substrate (110) having first and second portions (111, 112) with a first conductivity type, a transistor (120) at least partially located in the semiconductor substrate, and a switching circuit (150, 350, 650, 850). The transistor includes (i) a first doped region in the first portion of the semiconductor substrate and having the first conductivity type (ii) a terminal, which includes a second doped region having a second conductivity type and located in the first portion of the semiconductor substrate and over the first doped region, and (iii) a third doped region having the second conductivity type and located in the semiconductor substrate below the first portion of the semiconductor substrate and above the second portion of the semiconductor substrate. The switching circuit is electrically coupled to the third doped region to adjust the bias of the third doped region.