Patents by Inventor Visvesvaraya Appala Pentakota
Visvesvaraya Appala Pentakota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11936346Abstract: A low noise amplifier for an RF sampling analog front end. The amplifier includes digital step attenuation for applying a selected attenuation to signals received at an input node, and a gain stage coupled to amplify the attenuated signal from the digital step attenuation circuit. In a differential amplifier implementation, a first input capacitor is coupled between a positive side input node and an output of the negative side digital attenuation circuit, and a second input capacitor is coupled between a negative side input node and an output of the positive side digital step attenuation circuit. In some embodiments, variable feedback circuits are coupled between each input node and an output of the corresponding gain stage, to selectively apply active termination at the input at high gain settings of the amplifier. Variable input and output resistors, and programmable noise filtering at the output, are provided in some embodiments.Type: GrantFiled: April 15, 2021Date of Patent: March 19, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rahul Sharma, Jagannathan Venkataraman, Sandeep Oswal, Visvesvaraya Appala Pentakota
-
Patent number: 11916567Abstract: An example sample-and-hold circuit includes a first and second input resistors, each having first and second terminals; first and second transistors coupled in series between the second terminals of the first and second input resistors; and third and fourth input resistors, each having first and second terminals; and third and fourth transistors coupled in series between the second terminals of the third and fourth input resistors. A first capacitor is coupled between the first and second transistors and a second capacitor is coupled between the third and fourth transistors. The control terminals of the first and third transistors are coupled together, and the control terminals of the second and fourth transistors are coupled together.Type: GrantFiled: January 7, 2022Date of Patent: February 27, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sai Aditya Krishnaswamy Nurani, Joseph Palackal Mathew, Prasanth K, Visvesvaraya Appala Pentakota, Shagun Dusad
-
Patent number: 11881867Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.Type: GrantFiled: September 7, 2021Date of Patent: January 23, 2024Assignee: Texas Instruments IncorporatedInventors: Narasimhan Rajagopal, Eeshan Miglani, Chirag Chandrahas Shetty, Neeraj Shrivastava, Shagun Dusad, Srinivas Kumar Reddy Naru, Nithin Gopinath, Charls Babu, Shivam Srivastava, Viswanathan Nagarajan, Jagannathan Venkataraman, Harshit Moondra, Prasanth K, Visvesvaraya Appala Pentakota
-
Patent number: 11689210Abstract: An example apparatus includes: an analog input; a resistor circuit including a first reference output and a second reference output; a first amplifier including a first analog input, a first reference input, and a first amplifier output, the first analog input coupled to the analog input, the first reference input coupled to the first reference output; a second amplifier including a second analog input, a second reference input, and a second amplifier output, the second analog input coupled to the analog input, the second reference input coupled to the second reference output; a first comparator including a first comparator input, the first comparator input coupled to the first amplifier output; and a second comparator including a second comparator input, the second comparator input coupled to the second amplifier output; a first multiplexer including a first multiplexer input and a first residue output, the first multiplexer input coupled to the first amplifier output; and a second multiplexer including a seType: GrantFiled: October 29, 2021Date of Patent: June 27, 2023Assignee: Texas Instruments IncorporatedInventors: Prasanth K, Srinivas Kumar Reddy Naru, Visvesvaraya Appala Pentakota
-
Publication number: 20230138266Abstract: An example apparatus includes: an analog input; a resistor circuit including a first reference output and a second reference output; a first amplifier including a first analog input, a first reference input, and a first amplifier output, the first analog input coupled to the analog input, the first reference input coupled to the first reference output; a second amplifier including a second analog input, a second reference input, and a second amplifier output, the second analog input coupled to the analog input, the second reference input coupled to the second reference output; a first comparator including a first comparator input, the first comparator input coupled to the first amplifier output; and a second comparator including a second comparator input, the second comparator input coupled to the second amplifier output; a first multiplexer including a first multiplexer input and a first residue output, the first multiplexer input coupled to the first amplifier output; and a second multiplexer including a seType: ApplicationFiled: October 29, 2021Publication date: May 4, 2023Inventors: Prasanth K, Srinivas Kumar Reddy Naru, Visvesvaraya Appala Pentakota
-
Publication number: 20220337203Abstract: A low noise amplifier for an RF sampling analog front end. The amplifier includes digital step attenuation for applying a selected attenuation to signals received at an input node, and a gain stage coupled to amplify the attenuated signal from the digital step attenuation circuit. In a differential amplifier implementation, a first input capacitor is coupled between a positive side input node and an output of the negative side digital attenuation circuit, and a second input capacitor is coupled between a negative side input node and an output of the positive side digital step attenuation circuit. In some embodiments, variable feedback circuits are coupled between each input node and an output of the corresponding gain stage, to selectively apply active termination at the input at high gain settings of the amplifier. Variable input and output resistors, and programmable noise filtering at the output, are provided in some embodiments.Type: ApplicationFiled: April 15, 2021Publication date: October 20, 2022Inventors: Rahul Sharma, Jagannathan Venkataraman, Sandeep Oswal, Visvesvaraya Appala Pentakota
-
Publication number: 20220271764Abstract: A voltage-to-delay converter converts input signals into delay signals, and includes: a first stage for receiving the input signals and for generating intermediate output signals, wherein timing of the intermediate output signals corresponds to voltages of the input signals, and wherein the first stage has a voltage source for providing a rail-to-rail voltage; and a second stage for receiving the intermediate output signals and for generating rail-to-rail output signals, wherein timing of the rail-to-rail output signals corresponds to the timing of the intermediate output signals, and wherein voltage of the rail-to-rail output signals corresponds to the rail-to-rail voltage. A voltage-to-delay converter block is also described. A circuit for receiving differential input signals, generating corresponding output signals, and removing common mode signals from the output signals is also described.Type: ApplicationFiled: February 23, 2021Publication date: August 25, 2022Inventors: Prasanth K, Eeshan MIGLANI, Visvesvaraya Appala PENTAKOTA, Kartik GOEL, Jagannathan VENKATARAMAN, Sai Aditya Krishnaswamy NURANI
-
Patent number: 11424758Abstract: An analog-to-digital converter (ADC) having an input operable to receive an input voltage, VIN, and an output operable to output a digital code representative of VIN, the ADC including: a voltage-to-delay circuit having an input and an output, the input of the voltage-to-delay circuit coupled to the input of the ADC; a folding circuit having an input and an output, the input of the folding circuit coupled to the output of the voltage-to-delay circuit; and a time delay-based analog-to-digital converter backend having an input and a digital code output coupled to the output of the ADC, the input of the time delay-based analog-to-digital converter backend coupled to the output of the folding circuit.Type: GrantFiled: May 4, 2021Date of Patent: August 23, 2022Assignee: Texas Instruments IncorporatedInventors: Shagun Dusad, Chirag Chandrahas Shetty, Visvesvaraya Appala Pentakota
-
Publication number: 20220247421Abstract: In described examples, a circuit includes a multiplexer. The multiplexer receives an input voltage and a calibration signal. An analog-to-digital converter (ADC) is coupled to the multiplexer and generates an output code in response to the calibration signal. A storage circuit is coupled to the ADC and stores the input code representative of the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value.Type: ApplicationFiled: January 31, 2022Publication date: August 4, 2022Inventors: Visvesvaraya Appala Pentakota, Srinivas Kumar Reddy Naru, Chirag Shetty, Eeshan Miglani, Neeraj Shrivastava, Narasimhan Rajagopal, Shagun Dusad
-
Publication number: 20220247420Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.Type: ApplicationFiled: September 7, 2021Publication date: August 4, 2022Inventors: Narasimhan Rajagopal, Eeshan Miglani, Chirag Chandrahas Shetty, Neeraj Shrivastava, Shagun Dusad, Srinivas Kumar Reddy Naru, Nithin Gopinath, Charls Babu, Shivam Srivastava, Viswanathan Nagarajan, Jagannathan Venkataraman, Harshit Moondra, Prasanth K, Visvesvaraya Appala Pentakota
-
Patent number: 11387840Abstract: A system for converting a voltage into output codes includes logic gates for processing delay signals based on earlier and later arriving signals generated by preamplifiers, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits of the codes, and an auxiliary delay comparator for generating an auxiliary digital signal for use in generating the output codes. A system may include logic gates for generating delay signals based on earlier and later arriving signals, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits, and a multiplexer system for transmitting a selected one of the residue signals.Type: GrantFiled: December 21, 2020Date of Patent: July 12, 2022Assignee: Texas Instruments IncorporatedInventors: Eeshan Miglani, Visvesvaraya Appala Pentakota, Chirag Chandrahas Shetty
-
Publication number: 20220200620Abstract: A system for converting a voltage into output codes includes logic gates for processing delay signals based on earlier and later arriving signals generated by preamplifiers, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits of the codes, and an auxiliary delay comparator for generating an auxiliary digital signal for use in generating the output codes. A system may include logic gates for generating delay signals based on earlier and later arriving signals, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits, and a multiplexer system for transmitting a selected one of the residue signals.Type: ApplicationFiled: December 21, 2020Publication date: June 23, 2022Inventors: Eeshan MIGLANI, Visvesvaraya Appala PENTAKOTA, Chirag Chandrahas SHETTY
-
Publication number: 20220131551Abstract: An example sample-and-hold circuit includes a first and second input resistors, each having first and second terminals; first and second transistors coupled in series between the second terminals of the first and second input resistors; and third and fourth input resistors, each having first and second terminals; and third and fourth transistors coupled in series between the second terminals of the third and fourth input resistors. The control terminals of the first and third transistors are coupled together, and the control terminals of the second and fourth transistors are coupled together.Type: ApplicationFiled: January 7, 2022Publication date: April 28, 2022Inventors: Sai Aditya Krishnaswamy NURANI, Joseph Palackal MATHEW, Prasanth K., Visvesvaraya Appala PENTAKOTA, Shagun DUSAD
-
Patent number: 11316526Abstract: An analog-to-digital converter includes a voltage-to-delay device, such as a pre-amplifier array, for generating a delay signal based on a first voltage, and delay-based stages for generating digital signals based on the delay signal. In operation, the delay signal is transmitted to a first delay-based stage, or to an intermediate delay-based stage, bypassing the first delay-based stage, to overcome non-linearity of previous stages. If desired, different pre-amplifiers may be used to generate signals for calibration of different delay-based stages. The present disclosure may also involve converting to pseudo-static signals before signals are handed over to a calibration engine, to ease timing and preserve interface area and power. If desired, simple delay elements may be used to correct for non-linearity in a delay-based analog-to-digital converter. The present disclosure may be employed, if desired, in connection with any suitable cascade of non-linear stages.Type: GrantFiled: December 18, 2020Date of Patent: April 26, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Narasimhan Rajagopal, Visvesvaraya Appala Pentakota, Eeshan Miglani
-
Patent number: 11316525Abstract: An analog-to-digital converter system includes a digital-to-analog converter for generating calibration voltages based on digital input codes, and an analog-to-digital converter, connected to the digital-to-analog converter, for receiving the calibration voltages from the digital-to-analog converter, for receiving sampled voltages, for generating digital output codes based on the calibration voltages, and for generating digital output codes based on the sampled voltages. The analog-to-digital converter system may have a lookup table, connected to the analog-to-digital converter, for storing the first digital output codes in association with the digital input codes. A method of calibrating an analog-to-digital converter system is also disclosed.Type: GrantFiled: January 26, 2021Date of Patent: April 26, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Visvesvaraya Appala Pentakota, Narasimhan Rajagopal, Chirag Chandrahas Shetty, Prasanth K, Neeraj Shrivastava, Eeshan Miglani, Jagannathan Venkataraman
-
Patent number: 11309902Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.Type: GrantFiled: December 16, 2019Date of Patent: April 19, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srinivas Kumar Reddy Naru, Narasimhan Rajagopal, Shagun Dusad, Viswanathan Nagarajan, Visvesvaraya Appala Pentakota
-
Patent number: 11309903Abstract: A dynamic voltage-to-delay device may have voltage lines for receiving input signals during reset phases, and a current source, connected to the first and second voltage lines, for increasing voltages on the voltage lines during active phases. The voltage-to-delay device may also have comparators, connected to the voltage lines, for generating first and second output signals during the active phases when the voltages on the voltage lines reach a threshold voltage, such that a delay between the output signals is representative of a difference between voltages of the input signals. The voltage-to-delay device may have at least two current sources. The comparators may have a tail node to which a voltage is applied during a reset phase, and a current source for reducing the voltage at the tail node, and thereby reducing a threshold voltage during an active phase.Type: GrantFiled: December 23, 2020Date of Patent: April 19, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Eeshan Miglani, Visvesvaraya Appala Pentakota, Jagannathan Venkataraman
-
Patent number: 11277145Abstract: A sample-and-hold circuit includes a first input resistor, a first transistor, a first capacitor, a second resistor, and a first current source device. A first current terminal of the first transistor is coupled to the first input resistor. A first terminal of the first capacitor is coupled to the second current terminal of the first transistor at a first output node. A first terminal of the second resistor is coupled to the second terminal of the first transistor at the first output node. The first current source device is coupled the first input resistor and to the first current terminal of the first transistor.Type: GrantFiled: April 16, 2020Date of Patent: March 15, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sai Aditya Krishnaswamy Nurani, Joseph Palackal Mathew, Prasanth K, Visvesvaraya Appala Pentakota, Shagun Dusad
-
Patent number: 11239851Abstract: A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.Type: GrantFiled: August 20, 2020Date of Patent: February 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srinivas Kumar Reddy Naru, Anand Jerry George, Shagun Dusad, Visvesvaraya Appala Pentakota
-
Publication number: 20210328595Abstract: A sample-and-hold circuit includes a first input resistor, a first transistor, a first capacitor, a second resistor, and a first current source device. A first current terminal of the first transistor is coupled to the first input resistor. A first terminal of the first capacitor is coupled to the second current terminal of the first transistor at a first output node. A first terminal of the second resistor is coupled to the second terminal of the first transistor at the first output node. The first current source device is coupled the first input resistor and to the first current terminal of the first transistor.Type: ApplicationFiled: April 16, 2020Publication date: October 21, 2021Inventors: Sai Aditya Krishnaswamy NURANI, Joseph Palackal MATHEW, Prasanth K, Visvesvaraya Appala PENTAKOTA, Shagun DUSAD