Patents by Inventor Visvesvaraya Appala Pentakota
Visvesvaraya Appala Pentakota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210258018Abstract: An analog-to-digital converter (ADC) having an input operable to receive an input voltage, VIN, and an output operable to output a digital code representative of VIN, the ADC including: a voltage-to-delay circuit having an input and an output, the input of the voltage-to-delay circuit coupled to the input of the ADC; a folding circuit having an input and an output, the input of the folding circuit coupled to the output of the voltage-to-delay circuit; and a time delay-based analog-to-digital converter backend having an input and a digital code output coupled to the output of the ADC, the input of the time delay-based analog-to-digital converter backend coupled to the output of the folding circuit.Type: ApplicationFiled: May 4, 2021Publication date: August 19, 2021Inventors: Shagun DUSAD, Chirag Chandrahas SHETTY, Visvesvaraya Appala PENTAKOTA
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Patent number: 11031947Abstract: An RF receiver including: a low noise amplifier adapted to be coupled to an antenna and having an output; a bandpass filter coupled to the output of the low noise amplifier and having a voltage signal output, VIN; a conversion and folding circuit; and an analog-to-digital converter for converting the earlier-arriving or later-arriving delay signals into a digital code representing the voltage signal. The conversion and folding circuit including: a voltage-to-delay converter block, including preamplifiers, for converting the voltage signal into delay signals; and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals.Type: GrantFiled: April 28, 2020Date of Patent: June 8, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shagun Dusad, Chirag Chandrahas Shetty, Visvesvaraya Appala Pentakota
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Patent number: 10903845Abstract: A clock-less delay comparator coupled to a first input signal and a second input signal, the clock-less delay comparator comprising: a first transistor having a control terminal coupled to the second input signal, a first current terminal coupled to a first voltage supply, and a second current terminal; a second transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a third transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fourth transistor having a control terminal coupled to the first input signal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fifth transistor having a control terminal coupled to the second input signal, a first current terminal, and a second current terminal coupled to the control terminal of the third transistor; a sixth transistor having a control terminal coupled to the first inputType: GrantFiled: July 29, 2020Date of Patent: January 26, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Visvesvaraya Appala Pentakota, Rishi Soundararajan, Shagun Dusad, Chirag Chandrahas Shetty
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Publication number: 20200382128Abstract: A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.Type: ApplicationFiled: August 20, 2020Publication date: December 3, 2020Inventors: Srinivas Kumar Reddy NARU, Anand Jerry GEORGE, Shagun DUSAD, Visvesvaraya Appala PENTAKOTA
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Publication number: 20200358450Abstract: A clock-less delay comparator coupled to a first input signal and a second input signal, the clock-less delay comparator comprising: a first transistor having a control terminal coupled to the second input signal, a first current terminal coupled to a first voltage supply, and a second current terminal; a second transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a third transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fourth transistor having a control terminal coupled to the first input signal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fifth transistor having a control terminal coupled to the second input signal, a first current terminal, and a second current terminal coupled to the control terminal of the third transistor; a sixth transistor having a control terminal coupled to the first inputType: ApplicationFiled: July 29, 2020Publication date: November 12, 2020Inventors: Visvesvaraya Appala PENTAKOTA, Rishi SOUNDARARAJAN, Shagun DUSAD, Chirag Chandrahas SHETTY
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Patent number: 10790841Abstract: A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.Type: GrantFiled: December 14, 2018Date of Patent: September 29, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srinivas Kumar Reddy Naru, Anand Jerry George, Shagun Dusad, Visvesvaraya Appala Pentakota
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Patent number: 10778243Abstract: An analog-to-digital converter, comprising: a voltage to delay circuit having a voltage input, a threshold voltage input, a first output and a second output, wherein a leading edge of the first output is delayed, by a first delay magnitude, in relationship to a leading edge of the second output; and a first stage including: a first logic gate having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, and an output; and a first stage delay comparator having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, a sign signal output and a first stage delay comparator output, wherein the sign signal output represents whether the voltage input is greater than or less than the threshold voltage input.Type: GrantFiled: April 28, 2020Date of Patent: September 15, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Visvesvaraya Appala Pentakota, Rishi Soundararajan, Shagun Dusad, Chirag Chandrahas Shetty
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Publication number: 20200259501Abstract: An analog-to-digital converter, comprising: a voltage to delay circuit having a voltage input, a threshold voltage input, a first output and a second output, wherein a leading edge of the first output is delayed, by a first delay magnitude, in relationship to a leading edge of the second output; and a first stage including: a first logic gate having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, and an output; and a first stage delay comparator having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, a sign signal output and a first stage delay comparator output, wherein the sign signal output represents whether the voltage input is greater than or less than the threshold voltage input.Type: ApplicationFiled: April 28, 2020Publication date: August 13, 2020Inventors: Visvesvaraya Appala PENTAKOTA, Rishi SOUNDARARAJAN, Shagun DUSAD, Chirag Chandrahas SHETTY
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Publication number: 20200259502Abstract: An RF receiver including: an antenna cable of receiving an RF signal; a low noise amplifier coupled to the antenna and having an output; a bandpass filter coupled to the output of the low noise amplifier and having a voltage signal output, VIN; a conversion and folding circuit; and an analog-to-digital converter for converting the earlier-arriving or later-arriving delay signals into a digital code representing the voltage signal.Type: ApplicationFiled: April 28, 2020Publication date: August 13, 2020Inventors: Shagun DUSAD, Chirag Chandrahas SHETTY, Visvesvaraya Appala PENTAKOTA
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Patent number: 10673453Abstract: An analog-to-digital converter has a logic gate for generating an output signal having a delay corresponding to a delay between input signals. The logic gate includes inputs for receiving the input signals, and an output for outputting the output signal. A delay comparator generates a digital signal representative of the order of the input signals, and generates a delay signal having a delay corresponding to the delay between the input signals. The delay comparator has inputs for receiving the input signals, a digital output for outputting the digital signal, and a delay output for outputting the delay signal. A delay-based analog-to-digital converter, with a front stage and successive residual stages, is also disclosed. A delay comparator having merged comparator, sign-out, and delay-out circuits, and which may be operated within one of successive stages, without a clock, is also disclosed.Type: GrantFiled: July 22, 2019Date of Patent: June 2, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Visvesvaraya Appala Pentakota, Rishi Soundararajan, Shagun Dusad, Chirag Chandrahas Shetty
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Patent number: 10673456Abstract: A conversion and folding circuit includes a voltage-to-delay converter block, including preamplifiers, for converting a voltage signal into delay signals, and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals. If desired, the logic gates may include odd and even chains for outputting delay signals to first and second analog-to-digital converters. If desired, the conversion and folding circuit may include first and second chains, and a chain selection circuit for selectively outputting a delay signal from a desired one of the first and second chains.Type: GrantFiled: May 13, 2019Date of Patent: June 2, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shagun Dusad, Chirag Chandrahas Shetty, Visvesvaraya Appala Pentakota
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Publication number: 20200136631Abstract: A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.Type: ApplicationFiled: December 14, 2018Publication date: April 30, 2020Inventors: Srinivas Kumar Reddy NARU, Anand Jerry GEORGE, Shagun DUSAD, Visvesvaraya Appala PENTAKOTA
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Publication number: 20200119743Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Srinivas Kumar Reddy NARU, Narasimhan RAJAGOPAL, Shagun DUSAD, Viswanathan NAGARAJAN, Visvesvaraya Appala PENTAKOTA
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Patent number: 10601438Abstract: A modulator of an analog to digital converter includes a quantizer component configured to generate a digital signal based on a clock input operating at a sample rate. The modulator further includes a first digital to analog converter (DAC) configured to generate first DAC output at half the sample rate. The modulator further includes a second DAC configured to generate second DAC output at half the sample rate, where the first DAC and the second DAC are updated at alternate cycles of the clock input.Type: GrantFiled: June 7, 2019Date of Patent: March 24, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Eeshan Miglani, Visvesvaraya Appala Pentakota
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Patent number: 10541700Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.Type: GrantFiled: January 16, 2019Date of Patent: January 21, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Srinivas Kumar Reddy Naru, Narasimhan Rajagopal, Shagun Dusad, Viswanathan Nagarajan, Visvesvaraya Appala Pentakota
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Patent number: 10523231Abstract: A pipelined analog-to-digital converter (ADC) circuit includes a first ADC stage and a residue stage coupled to the first ADC stage. The residue stage includes a dynamic integrator configured to provide transconductance, wherein the dynamic integrator includes a boost circuit configured to boost an output impedance of the transconductance.Type: GrantFiled: December 27, 2018Date of Patent: December 31, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sai Aditya KrishnaSwamy Nurani, Shagun Dusad, Visvesvaraya Appala Pentakota
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Publication number: 20190379391Abstract: A modulator of an analog to digital converter includes a quantizer component configured to generate a digital signal based on a clock input operating at a sample rate. The modulator further includes a first digital to analog converter (DAC) configured to generate first DAC output at half the sample rate. The modulator further includes a second DAC configured to generate second DAC output at half the sample rate, where the first DAC and the second DAC are updated at alternate cycles of the clock input.Type: ApplicationFiled: June 7, 2019Publication date: December 12, 2019Inventors: Eeshan MIGLANI, Visvesvaraya Appala PENTAKOTA
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Publication number: 20190280703Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.Type: ApplicationFiled: January 16, 2019Publication date: September 12, 2019Inventors: Srinivas Kumar Reddy NARU, Narasimhan RAJAGOPAL, Shagun DUSAD, Viswanathan NAGARAJAN, Visvesvaraya Appala PENTAKOTA
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Patent number: 8920326Abstract: A mixer circuit includes three square wave mixers and a combiner. A first square wave mixer in the circuit multiplies an input signal with a first square wave. A second square wave mixer and a third square wave mixer in the circuit each multiplies the input signal with a second square wave and a third square wave respectively. The second and third square waves have a same frequency as the first square wave, but phases that respectively lead and lag the phase of the first square wave by a first value. The combiner adds the outputs of the mixers. A low-pass filter external to the mixer circuit filters the sum generated by the combiner to generate a filtered output. In an embodiment, the first value equals forty five degrees, and the filtered output is rendered free of products generated by third and fifth harmonics of the first square wave square.Type: GrantFiled: August 12, 2011Date of Patent: December 30, 2014Assignee: Texas Instruments IncorporatedInventors: Vajeed Nimran P A, Shabbir Amjhera Wala, Shagun Dusad, Sandeep Oswal, Visvesvaraya Appala Pentakota
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Publication number: 20130039151Abstract: A mixer circuit includes three square wave mixers and a combiner. A first square wave mixer in the circuit multiplies an input signal with a first square wave. A second square wave mixer and a third square wave mixer in the circuit each multiplies the input signal with a second square wave and a third square wave respectively. The second and third square waves have a same frequency as the first square wave, but phases that respectively lead and lag the phase of the first square wave by a first value. The combiner adds the outputs of the mixers. A low-pass filter external to the mixer circuit filters the sum generated by the combiner to generate a filtered output. In an embodiment, the first value equals forty five degrees, and the filtered output is rendered free of products generated by third and fifth harmonics of the first square wave square.Type: ApplicationFiled: August 12, 2011Publication date: February 14, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Vajeed Nimran P. A., Shabbir Amjhera Wala, Shagun Dusad, Sandeep Oswal, Visvesvaraya Appala Pentakota