Patents by Inventor Visvesvaraya Pentakota

Visvesvaraya Pentakota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190273601
    Abstract: A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.
    Type: Application
    Filed: May 21, 2019
    Publication date: September 5, 2019
    Inventors: Jaiganesh BALAKRISHNAN, Shagun DUSAD, Visvesvaraya PENTAKOTA, Srinivas Kumar Reddy NARU, Sarma Sundareswara GUNTURI, Nagalinga Swamy Basayya AREMALLAPUR
  • Patent number: 10367511
    Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: July 30, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shagun Dusad, Visvesvaraya Pentakota, Mark Baxter Weaver, William Bright, Jiankun Hu
  • Publication number: 20190222207
    Abstract: A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.
    Type: Application
    Filed: March 26, 2019
    Publication date: July 18, 2019
    Inventors: Rishi SOUNDARARAJAN, Visvesvaraya PENTAKOTA
  • Patent number: 10341082
    Abstract: A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: July 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaiganesh Balakrishnan, Shagun Dusad, Visvesvaraya Pentakota, Srinivas Kumar Reddy Naru, Sarma Sundareswara Gunturi, Nagalinga Swamy Basayya Aremallapur
  • Patent number: 10320405
    Abstract: In described examples, an analog to digital converter (ADC) includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota Appala, Shagun Dusad, Neeraj Shrivastava, Viswanathan Nagarajan, Ani Xavier, Rishi Soundararajan, Sai Aditya Nurani, Roswald Francis
  • Patent number: 10284188
    Abstract: A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: May 7, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rishi Soundararajan, Visvesvaraya Pentakota
  • Patent number: 10185339
    Abstract: A voltage regulator that provides feedforward cancellation of power supply noise is disclosed. The voltage regulator includes a process tracking circuit that receives a supply voltage and generates a proportional voltage. A tracking capacitor is coupled to the process tracking circuit and generates an injection voltage based on the proportional voltage. An Ahuja compensated regulator generates a regulated voltage. The injection voltage is provided on a feedback path of the Ahuja compensated regulator.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: January 22, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shuaeb Fazeel, Eeshan Miglani, Visvesvaraya Pentakota, Shagun Dusad
  • Publication number: 20180323790
    Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.
    Type: Application
    Filed: July 16, 2018
    Publication date: November 8, 2018
    Inventors: Shagun DUSAD, Visvesvaraya PENTAKOTA, Mark Baxter WEAVER, William BRIGHT, Jiankun HU
  • Patent number: 10050632
    Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: August 14, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shagun Dusad, Visvesvaraya Pentakota, Mark Baxter Weaver, William Bright, Jiankun Hu
  • Patent number: 10038453
    Abstract: An analog-to-digital converter includes a comparator, a capacitive digital-to-analog converter (DAC), and calibration circuitry. The capacitive DAC is coupled to the comparator, and includes a plurality of capacitors. The calibration circuitry is configured to adjust a value of each of the capacitors, and includes binary search circuitry and error correction circuitry. The binary search circuitry applies a binary search over a first number of bits of a multi-bit adjustment value used to adjust the value of one of the capacitors, and averages a first number of comparator output samples to determine each of the first number of bits. The error correction circuitry applies an error correction to the multi-bit adjustment value generated by the binary search, and averages a second number of comparator output samples for the error correction. The second number of comparator output samples is greater than the first number of comparator output samples.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: July 31, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anand Jerry George, Rishi Soundararajan, Visvesvaraya Pentakota
  • Publication number: 20180191355
    Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Shagun DUSAD, Visvesvaraya PENTAKOTA, Mark Baxter WEAVER, William BRIGHT, Jiankun HU
  • Publication number: 20180191362
    Abstract: The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.
    Type: Application
    Filed: March 1, 2018
    Publication date: July 5, 2018
    Inventors: Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota Appala, Shagun Dusad, Neeraj Shrivastava, Viswanathan Nagarajan, Ani Xavier, Rishi Soundararajan, Sai Aditya Nurani, Roswald Francis
  • Publication number: 20180183409
    Abstract: The disclosure provides an RF receiver. The RF receiver includes an input driver. The input driver receives a coarse signal, and generates an input signal. A digital step attenuator (DSA) is coupled to the input driver and receives the input signal. An analog to digital converter (ADC) is coupled to the DSA. The DSA includes a serial capacitor coupled to the input driver. The DSA also includes a sampling capacitor coupled to the ADC.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 28, 2018
    Inventors: Rajendrakumar Joish, Visvesvaraya Pentakota
  • Patent number: 9941893
    Abstract: An ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: April 10, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota Appala, Shagun Dusad, Neeraj Shrivastava, Viswanathan Nagarajan, Ani Xavier, Rishi Soundararajan, Sai Aditya Nurani, Roswald Francis
  • Publication number: 20170302287
    Abstract: The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.
    Type: Application
    Filed: April 12, 2017
    Publication date: October 19, 2017
    Inventors: Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota Appala, Shagun Dusad, Neeraj Shrivastava, Viswanathan Nagarajan, Ani Xavier, Rishi Soundararajan, Sai Aditya Nurani, Roswald Francis
  • Patent number: 9748965
    Abstract: Disclosed examples include pipeline ADC, balancing circuits and methods to balance a load of a reference circuit to reduce non-linearity and settling effects for a reference voltage signal, in which balancing capacitors are connected to a voltage source in a pipeline stage ADC sample time period to precharge the balancing capacitors using a voltage above the reference voltage, and a selected set of the precharged balancing capacitors is connected to provide charge to the output of the reference circuit during the second time period.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: August 29, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Roswald Francis, Visvesvaraya A. Pentakota
  • Publication number: 20170041014
    Abstract: The disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.
    Type: Application
    Filed: February 19, 2016
    Publication date: February 9, 2017
    Inventors: Neeraj SHRIVASTAVA, Supreet JOSHI, Himanshu VARSHNEY, Jafar Sadique KAVILADATH, Visvesvaraya PENTAKOTA, Shagun DUSAD
  • Patent number: 9548752
    Abstract: The disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: January 17, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATION
    Inventors: Neeraj Shrivastava, Supreet Joshi, Himanshu Varshney, Jafar Sadique Kaviladath, Visvesvaraya Pentakota, Shagun Dusad
  • Publication number: 20160315629
    Abstract: In described examples, an analog to digital converter (ADC) includes a main ADC and a reference ADC. The main ADC generates a zone information signal and a digital output in response to an input signal. The reference ADC receives a plurality of reference voltages from the main ADC. The plurality of reference voltages includes a first reference voltage and a second reference voltage. The reference ADC generates a reference output in response to the input signal, the first reference voltage and the second reference voltage. A subtractor generates an error signal in response to the digital output and the reference output. A logic block generates one of a first offset correction signal, a second offset correction signal and a gain mismatch signal in response to the zone information signal, the error signal and the reference output.
    Type: Application
    Filed: September 30, 2015
    Publication date: October 27, 2016
    Inventors: Srinivas Kumar Reddy NARU, Nagarajan VISWANATHAN, Visvesvaraya PENTAKOTA
  • Patent number: 9479186
    Abstract: In described examples, an analog to digital converter (ADC) includes a main ADC and a reference ADC. The main ADC generates a zone information signal and a digital output in response to an input signal. The reference ADC receives a plurality of reference voltages from the main ADC. The plurality of reference voltages includes a first reference voltage and a second reference voltage. The reference ADC generates a reference output in response to the input signal, the first reference voltage and the second reference voltage. A subtractor generates an error signal in response to the digital output and the reference output. A logic block generates one of a first offset correction signal, a second offset correction signal and a gain mismatch signal in response to the zone information signal, the error signal and the reference output.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: October 25, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivas Kumar Reddy Naru, Nagarajan Viswanathan, Visvesvaraya Pentakota