Abstract: An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.

Abstract: An analog-to-digital converter circuit module utilizing dither to reduce multiplicative noise. A dither generation circuit generates a noise-shaped analog dither signal having lower amplitudes at frequencies below a cutoff frequency than at frequencies above the cutoff frequency. The noise-shaped analog dither signal is added to the input analog signal to be converted and the summed signal applied to an analog-to-digital converter The dither generation circuit may be implemented as an analog dither generator followed by an analog high-pass filter. The dither generation circuit may alternatively be implemented digitally, for example with a digital noise-shaping filter applying a high-pass digital filter to a pseudo-random binary sequence. The digital dither generation circuit may alternatively be implemented by one or more 1-bit sigma-delta modulators, each generating a bit of a digital dither sequence that is converted to analog.

Abstract: One example includes an analog-to-digital converter (ADC) front-end system. The system includes a digital step attenuator (DSA) having an input and an output. The system also includes a sampling system having an input coupled to the output of the DSA. The sampling system includes a first sampling capacitor, a second sampling capacitor, and at least one sampling switch. The sampling system can be configured to sample an analog signal current provided from the DSA on the first sampling capacitor and the second sampling capacitor concurrently in response to activation of the at least one sampling switch to integrate the analog signal current as a sampling voltage on both the first and second sampling capacitors. The system further includes an ADC having an input and an output, the input of the ADC coupled to the output of the sampling system.

Abstract: An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.

Abstract: A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.

Abstract: A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.

Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

Abstract: An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.

Abstract: A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.

Abstract: An analog-to-digital converter circuit module utilizing dither to reduce multiplicative noise. A dither generation circuit generates a noise-shaped analog dither signal having lower amplitudes at frequencies below a cutoff frequency than at frequencies above the cutoff frequency. The noise-shaped analog dither signal is added to the input analog signal to be converted and the summed signal applied to an analog-to-digital converter The dither generation circuit may be implemented as an analog dither generator followed by an analog high-pass filter. The dither generation circuit may alternatively be implemented digitally, for example with a digital noise-shaping filter applying a high-pass digital filter to a pseudo-random binary sequence. The digital dither generation circuit may alternatively be implemented by one or more 1-bit sigma-delta modulators, each generating a bit of a digital dither sequence that is converted to analog.

Abstract: An analog-to-digital converter (ADC) including: a signal input adapted to receive an analog signal; a first reference voltage input adapted to receive a first reference voltage; a second reference voltage input adapted to receive a second reference voltage, the second reference voltage is different than the first reference voltage; a first delay circuit having a first delay input coupled to the signal input, a second delay input coupled to the first reference voltage input, a first delay output and a second delay output; a second delay circuit having a third delay input coupled to the signal input, a fourth delay input coupled to the second reference voltage input; a third delay output and a fourth delay output; a first comparator having a first comparator input coupled to the first delay output, a second comparator input coupled to the second delay output and a first comparator output; and a second comparator having a third comparator input coupled to the third delay output, a fourth comparator input coupled

Abstract: A radio frequency transmitter includes an upconverter that outputs in-phase (I) and quadrature (Q) signals, a digital timing offset circuit, first and second digital-to-analog converters (DACs), an analog timing offset removal circuit, first and second pulse shapers, and an adder. The digital timing offset circuit introduces a time offset between the I and Q signals. The first and second DACs output analog I and Q signals, respectively, and have first and second clock signals, respectively. The first and second clock signals have the same frequency and are offset relative to each other by the time offset. The analog timing offset removal circuit removes the time offset between the analog I and Q signals. The first and second pulse shapers receive the analog I and Q signals, respectively, and output pulse-shaped I and Q signals. The adder receives the pulse-shaped I and Q signals and outputs an intermediate frequency signal.

Abstract: In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

Abstract: An analog to digital converter (ADC) comprising: a delay circuit having a complementary signal output; a first comparator having an input coupled to the complementary signal output of the delay circuit, the first comparator having a first output and a second output; a first dummy comparator having a first dummy input coupled to the first output and a second dummy input coupled to the second output, the first dummy comparator having a dummy output; a first interpolation comparator having an interpolation output and a first interpolation input coupled to the first output; a second dummy comparator having an input coupled to the interpolation output; and a second interpolation comparator having a second interpolation input and a third interpolation input, the second interpolation input coupled to the interpolation output and the third interpolation input coupled to the dummy output.

Abstract: An analog-to-digital converter (ADC) including: a signal input adapted to receive an analog signal; a first reference voltage input adapted to receive a first reference voltage; a second reference voltage input adapted to receive a second reference voltage, the second reference voltage is different than the first reference voltage; a first delay circuit having a first delay input coupled to the signal input, a second delay input coupled to the first reference voltage input, a first delay output and a second delay output; a second delay circuit having a third delay input coupled to the signal input, a fourth delay input coupled to the second reference voltage input; a third delay output and a fourth delay output; a first comparator having a first comparator input coupled to the first delay output, a second comparator input coupled to the second delay output and a first comparator output; and a second comparator having a third comparator input coupled to the third delay output, a fourth comparator input coupled

Abstract: A method of converting an analog signal to a digital code, comprising: using a first comparator to receive an input signal and a first comparison signal, and to generate a first output as a function of the input signal and the first comparison signal; using a second comparator to receive the input signal and a second comparison signal, and to generate a second output as a function of the input signal and the second comparison signal; and using an interpolation comparator to receive the first and second outputs, and to generate a third output based on relative timing of the first and second outputs; further including multiplexing to permit a second-level comparator to receive timing signals from the interpolation comparator and only one of two dummy comparators.

Abstract: An analog to digital converter (ADC) comprising: a delay circuit having a complementary signal output; a first comparator having an input coupled to the complementary signal output of the delay circuit, the first comparator having a first output and a second output; a first dummy comparator having a first dummy input coupled to the first output and a second dummy input coupled to the second output, the first dummy comparator having a dummy output; a first interpolation comparator having an interpolation output and a first interpolation input coupled to the first output; a second dummy comparator having an input coupled to the interpolation output; and a second interpolation comparator having a second interpolation input and a third interpolation input, the second interpolation input coupled to the interpolation output and the third interpolation input coupled to the dummy output.

Abstract: A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.

Abstract: A transmitter for an RF communications system, that includes an auxiliary receiver for capturing transmit signal data for use in compensating/correcting transmit signal impairments (such as for DPD, QMC, LOL). The transmitter (such as Zero IF) includes analog chain elements that introduce transmit signal impairments (such as PA nonlinearities). The auxiliary receiver is configured to receive loopback transmit RF signals, and includes an RF direct sampling ADC to convert the loopback transmit RF signals to digital transmit RF signals. Digital down conversion circuitry is configured to downconvert the digital transmit RF signals to captured digital transmit baseband signals, and data capture circuitry is configured to generate the transmit signal data based on the captured digital transmit baseband signals.