Abstract: A low-noise output buffer for a digital signal is based on an analog amplifier having bandwidth greater than the switching rate of the digital logic signal. A converter circuit converts the digital logic signal to a ramp signal provided as an input to the analog amplifier. The ramp signal has a slope determined by a bias current and an input capacitance of the analog amplifier. The bias current is generated by a bias circuit such that the bias current varies as the input capacitance of the analog amplifier varies due to variations in the manufacturing process. Therefore, the slope of the ramp signal remains substantially constant despite the variations in the manufacturing process. In particular, the slope of the ramp signal is not undesirably steep even when the buffer is made by a worst-case “strong” process.

Abstract: Low voltage transistors are used in high voltage environment. The low voltage transistors may be used in the path of processing of a signal to increase the throughput performance. By using high voltage supply associated with the high voltage environment, a higher SNR may be attained. Various techniques are implemented to ensure that the low voltage transistors are not damaged by prolonged exposure to high voltages.

Abstract: An on-chip calibration circuit which can dynamically (i.e., in operational environment) measure the capacitor mismatch in an ADC using sampling capacitors to sample an input signal and a feedback capacitor (in combination with an amplifier) for amplification. The measured values can be used to generate accurate digital codes representing analog signal samples. The calibration circuit connects the capacitors to various voltage levels and measures the mismatch levels by examining various signals (e.g., the digital codes) generated in such situations.

Abstract: A resistor (or a component with impedance that does not change) is provided across the output of an amplifier, which minimizes the changes in the amplification factor of an amplification circuit during operation.

Abstract: The strength of the output buffer is changed gradually when there is a transition in the output (or input) value. Due to the gradual change, switching noise is avoided in several contexts (e.g., when driving a transmission line, which causes reflections). In an embodiment, the gradual change is implemented using a combination of a current source and a capacitor. The capacitor is provided at an input of the gate terminal of a drive transistor, and a current source is used to control the rate at which the capacitor discharges. As a result, the drive strength of a buffer is controlled.

Abstract: A clamping circuit containing a transistor and a current amplifier. The transistor is designed to turn on when the voltage at a node exceeds (falls below) a specified upper (lower) level. The current amplifier is designed to draw substantial amount of current when the transistor is turned on to clamp the voltage at the node to the desired level.

Abstract: An ADC implemented according to an aspect of the present invention contains a non-zero bit stage followed by a zero-bit stage. The non-zero bit stage generates a sub-code, which is used in generating a digital code corresponding to an input analog signal, and the zero-bit stage does not provide any such sub-codes. Such a feature may be attained by using a gain amplifier provided according to another aspect of the present invention. The gain amplifier contains a main-amplifier which operates as a zero bit stage, and is also used by the non-zero bit stage. The same capacitance value may be maintained between the input terminal and output terminal of the main-amplifier to implement the zero bit stage, which enables the main-amplifier to be implemented with a low gain.

Abstract: A delay locked loop clock generation circuit (100) includes a delay locked loop circuit (18), a dummy delay line (40), and a watch dog circuit (32). The delay locked loop circuit includes a delay line (20), a phase detector (25), and a charge pump circuit (30) having an input connected to the output (27) of the phase detector and an output (23) producing a delay control signal (Vctrl) coupled to the stages of the delay line of the delay locked loop circuit. The stages of the delay line are precisely matched to those of the dummy delay line (40). Tap points of the dummy delay line are connected to inputs of the watchdog circuit (32), which operates to generate control signals (34A,B) applied to control the phase detector (25 and the charge pump circuit (30). Tap point.signals of the delay line (20) are decoded to produce clock signals (52) for a pipeline ADC (54).

Abstract: To apply a desired voltage at a node driving a load impedance, a voltage source providing the desired voltage is connected to the node. In addition, a current source supplying an amount of current that would be drawn by the impedance if the voltage source alone were connected across the impedance. As a result, the voltage source may be freed substantially from supplying current, which may be advantageously used in several situations. For example, the approach can be used to connect a voltage source directly to a high load without potentially requiring a buffer between the voltage source and the node. Alternatively, the approach can be used to apply the same desired voltage at each of multiple nodes connected in series using the same voltage source without being affected by the routing resistance generally present between each pair of the nodes.

Abstract: An on-chip calibration circuit which can dynamically (i.e., in operational environment) measure the capacitor mismatch in an ADC using sampling capacitors to sample an input signal and a feedback capacitor (in combination with an amplifier) for amplification. The measured values can be used to generate accurate digital codes representing analog signal samples. The calibration circuit connects the capacitors to various voltage levels and measures the mismatch levels by examining various signals (e.g., the digital codes) generated in such situations.

Abstract: A bandwidth limited sampling circuit of high linearity may be implemented by using a first circuit portion to limit the bandwidth of the input signals, and using a second circuit portion to sample the bandwidth limited input signal. The first circuit portion and the second circuit portion may be implemented using separate components. In an alternative embodiment, bandwidth limiting is implemented by taking a difference of a sampled input signal from a sampled high frequency components of the input signal.

Abstract: An aspect of the present invention reduces droop in the reference signal provided to ADCs. A compensation resistor of appropriate resistance value is provided in the path of the reference signal to minimize the droop.

Abstract: Using an operational amplifier with a low gain in a closed loop amplifier circuit, and correcting for errors (i.e., deviation from the output of an ideal closed loop amplifier using an operational amplifier with infinite gain) that would result from the use of the operational amplifier with low gain. In an embodiment implemented in relation to an analog to digital converter (ADC), a mathematical operation is performed on the digital code(s) generated by the ADC to generate a corrected code corresponding to an analog sample.

Abstract: The rate at which the output of an output buffer changes is determined, and the strength of the output buffer is modified until the rate of change reaches a desired rate. The desired rate may be selected such that strength of the output buffer matches the then existing load. In other words, the strength may be only as much as needed to drive the then existing load. As a result, effects such as switching noise may be considerably reduced.

Abstract: An analog circuit 20 includes an amplifier 30 with a positive input node, a negative input node, a positive output node and a negative output node. A first capacitor 32 is coupled between the negative input node and an analog signal node. A second capacitor 34 is coupled between the positive input node and a reference voltage node. In addition, a third capacitor 36 is coupled between the positive input node and the negative output node and a fourth capacitor 38 is coupled between the negative input node and the positive output node. A first switch 40 is coupled between the third capacitor 36 and the negative output node and a second switch 42 is coupled between the fourth capacitor 38 and the positive output node. An inverter coupled to the analog signal node drives common mode capacitors coupled between the output of the inverter and the respective negative and positive input nodes.

Abstract: An analog circuit 20 includes an amplifier 30 with a positive input node, a negative input node, a positive output node and a negative output node. A first capacitor 32 is coupled between the negative input node and an analog signal node. A second capacitor 34 is coupled between the positive input node and a reference voltage node. In addition, a third capacitor 36 is coupled between the positive input node and the negative output node and a fourth capacitor 38 is coupled between the negative input node and the positive output node. A first switch 40 is coupled between the third capacitor 36 and the negative output node and a second switch 42 is coupled between the fourth capacitor 38 and the positive output node.

Abstract: An amplification circuit sharing a main amplifier in two gain stages while minimizing power consumption. A Miller Compensated Amplifier contains the main amplifier and a pre-amplifier, with the output of the pre-amplifier being connected to the input of the main amplifier. In a first gain stage, the two amplifiers together amplify an input signal. The main amplifier is then disconnected from the pre-amplifier in a second gain stage to further amplify the amplified signal of the first gain stage. A capacitor is configured to act as a compensation capacitor of the main amplifier in the first gain stage, and as a sampling capacitor in the second gain stage. The amplifier circuit may be implemented in an ADC of a digital camera.

Abstract: An amplification circuit sharing a main amplifier in two gain stages while minimizing power consumption. A Miller Compensated Amplifier contains the main amplifier and a pre-amplifier, with the output of the pre-amplifier being connected to the input of the main amplifier. In a first gain stage, the two amplifiers together amplify an input signal. The main amplifier is then disconnected from the pre-amplifier in a second gain stage to further amplify the amplified signal of the first gain stage. A capacitor is configured to act as a compensation capacitor of the main amplifier in the first gain stage, and as a sampling capacitor in the second gain stage. The amplifier circuit may be implemented in an ADC of a digital camera.