Patents by Inventor Vivek De

Vivek De has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

Operating an information storage cell array

Publication number: 20070002611

Abstract: A cell in an information storage cell array is written, by asserting a signal on a bit line that is coupled to the cell and to a group of other cells in the array, to a first voltage. The cell is read by asserting a signal on a word line that is coupled to the cell and to another group of cells in the array, in a direction of, but without reaching, the first voltage. Other embodiments are also described and claimed.

Type: Application

Filed: June 30, 2005

Publication date: January 4, 2007

Inventors: Yibin Ye, Muhammad Khellah, Dinesh Somasekhar, Ali Keshavarzi, Fabrice Paillet, Vivek De
Capacitor structure for a logic process

Publication number: 20070004162

Abstract: A manufacturing process modification is disclosed for producing a metal-insulator-metal (MIM) capacitor. The MIM capacitor may be used in memory cells, such as DRAMs, and may also be integrated into logic processing, such as for microprocessors. The processing used to generate the MIM capacitor is adaptable to current logic processing techniques. Other embodiments are described and claimed.

Type: Application

Filed: June 29, 2005

Publication date: January 4, 2007

Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Vivek De
Memory circuit

Publication number: 20070002607

Abstract: In some embodiments, a memory array is provided comprising columns of SRAM bit cells, the columns each comprising a bit line and a sense amplifier coupled to the bit line, the sense amplifier to maintain a state in a selected cell of its bit line during a read operation. Other embodiments are disclosed herein.

Type: Application

Filed: June 29, 2005

Publication date: January 4, 2007

Inventors: Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Vivek De
DC-DC converter switching transistor current measurement technique

Publication number: 20070001762

Abstract: A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair of transistors whose conductive channels are coupled in series with respect to each other and are together coupled in parallel across the switching transistor's conductive channel. The second current is less than and proportional to the first current.

Type: Application

Filed: June 30, 2005

Publication date: January 4, 2007

Inventors: Gerhard Schrom, Peter Hazucha, Vivek De, Tanay Karnik
Voltage regulation using digital voltage control

Publication number: 20060290547

Abstract: For one disclosed embodiment, error is sensed in a voltage at an output node. One or more analog signals are generated based on the sensed error. One or more generated analog signals are converted into one or more digital signals. The voltage at the output node is controlled in response to the one or more digital signals.

Type: Application

Filed: June 27, 2005

Publication date: December 28, 2006

Inventors: Peter Hazucha, Saravanan Rajapandian, Gerhard Schrom, Tanay Karnik, Vivek De
Memory cell driver circuits

Publication number: 20060291265

Abstract: A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.

Type: Application

Filed: June 27, 2005

Publication date: December 28, 2006

Inventors: Gerhard Schrom, Fabrice Paillet, Tanay Karnik, Dinesh Somasekhar, Yibin Ye, Ali Keshavarzi, Muhammad Khellah, Vivek De
Low-voltage, buffered bandgap reference with selectable output voltage

Publication number: 20060290415

Abstract: A temperature-independent voltage reference containing two independent bias circuits powered by the reference voltage, each bias circuit containing components with an exponential dependence of current on voltage and one containing a resistive impedance, and further including voltage dividers and an active component.

Type: Application

Filed: June 28, 2005

Publication date: December 28, 2006

Inventors: Peter Hazucha, Sung Moon, Gerhard Schrom, Fabrice Paillet, Tanay Karnik, Vivek De
APPARATUS AND METHOD FOR PROGRAMMING A MEMORY ARRAY

Publication number: 20060285393

Abstract: A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.

Type: Application

Filed: June 21, 2005

Publication date: December 21, 2006

Inventors: Fabrice Paillet, Ali Keshavarzi, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Stephen Tang, Mohsen Alavi, Vivek De, Tanay Karnik
Purge-based floating body memory

Publication number: 20060279985

Abstract: In general, in one aspect, the disclosure describes a memory array including a plurality of memory cells arranged in rows and columns. Each memory cell includes a transistor having a floating body capable of storing a charge. A plurality of word lines and purge lines are interconnected to rows of memory cells. A plurality of bit lines are interconnected to columns of memory cells. Driving signals provided via the word lines, the purge lines, and the bit lines can cooperate to alter the charge of the floating body region in one or more of the memory cells.

Type: Application

Filed: June 14, 2005

Publication date: December 14, 2006

Inventors: Ali Keshavarzi, Stephen Tang, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Vivek De, Gerhard Schrom
Floating-body dynamic random access memory and method of fabrication in tri-gate technology

Publication number: 20060267093

Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

Type: Application

Filed: May 4, 2006

Publication date: November 30, 2006

Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Brian Doyle, Suman Datta, Vivek De
Memory with dynamically adjustable supply

Publication number: 20060268626

Abstract: In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.

Type: Application

Filed: May 25, 2005

Publication date: November 30, 2006

Inventors: Fatih Hamzaoglu, Kevin Zhang, Nam Kim, Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Vivek De, Bo Zheng
Reducing power consumption in integrated circuits

Publication number: 20060262610

Abstract: A method and apparatus for reducing power consumption in integrated memory devices is provided. Banks of memory cells may be individually put into “sleep” mode via respective “sleep” transistors.

Type: Application

Filed: May 23, 2005

Publication date: November 23, 2006

Applicant: Intel Corporation

Inventors: Muhammad Khellah, Dinesh Somasekhar, Yibin Ye, Vivek De, James Tschanz, Stephen Tang
Method and apparatus for power consumption reduction

Publication number: 20060259890

Abstract: A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block having an edge-triggered circuit may be provided in a second area of the chip. Edge-triggered circuits within the second functional block may be replaced with dual edge-triggered circuits. Phase logic circuits may be clocked by a full frequency clock signal and dual edge-triggered circuits may be clocked by a half-frequency clock signal.

Type: Application

Filed: July 14, 2006

Publication date: November 16, 2006

Inventors: James Tschanz, Nasser Kurd, Javed Barkatullah, Vivek De
Method and apparatus to adjust die frequency

Publication number: 20060226863

Abstract: A method and apparatus are provided for adjusting a frequency of a die. This may include measuring characteristics of a die at various combinations of power supply voltage, body bias voltage and/or temperature and determining operating characteristics, such as power supply voltage and body bias voltage, based on the measured characteristics.

Type: Application

Filed: March 31, 2005

Publication date: October 12, 2006

Inventors: Siva Narendra, James Tschanz, Victor Zia, Badarinath Kommandur, Tawfik Arabi, Grant McFarland, Vivek De
Signal measurement systems and methods

Publication number: 20060220677

Abstract: Systems and methods are disclosed for measuring signals on an integrated circuit die. In one embodiment, a reference signal is distributed to die locations proximal to the signals to be measured. The reference signal is transmitted over transport paths coupling each of the signals to be measured to the die output. The signals to be measured are transmitted over their respective transport paths and measured at the die output. The relative delay between the signals can be calculated using the reference signal measurements.

Type: Application

Filed: March 31, 2005

Publication date: October 5, 2006

Applicant: Intel Corporation, A DELAWARE CORPORATION

Inventors: Peter Hazucha, Gerhard Schrom, Tanay Karnik, Vivek De
2-Transistor floating-body dram

Publication number: 20060187706

Abstract: A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.

Type: Application

Filed: February 22, 2005

Publication date: August 24, 2006

Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Vivek De
Representative majority voter for bus invert coding

Publication number: 20060184595

Abstract: In general, in one aspect, the disclosure describes an apparatus inluding a representative majority voter gate to analyze bit transitions of a pluraility of bits. The plurailuty of bits are analzed in groups. The representative majority voter gate generates an invert signal based on the analysis. The apparatus further inludes a conditional inverter to apply the invert signal to the pluraility of bits.

Type: Application

Filed: February 16, 2005

Publication date: August 17, 2006

Inventors: James Tschanz, Mircea Stan, Muhammad Khellah, Yibin Ye, Vivek De
Bias generator for body bias

Publication number: 20060164152

Abstract: A bias generator is provided that includes a central bias generator to provide a first bias voltage and a local bias generator to receive the first bias voltage and to provide a second bias voltage. The central bias generator may include a replica bias generator circuit substantially corresponding to the local bias generator.

Type: Application

Filed: January 21, 2005

Publication date: July 27, 2006

Inventors: James Tschanz, Stephen Tang, Victor Zia, Badarinath Kommandur, Siva Narendra, Vivek De
Bias generator for body bias

Publication number: 20060164157

Abstract: A bias generator unit is provided that includes a central bias generator to provide a bias voltage, a local bias generator to receive the bias voltage and a reference voltage and to provide a forward body bias signal or a reverse body bias signal. The bias generator may include a charge pump to output (or provide) a reference voltage to a reference generator, which in turn provides reference signals to the central bias generator. As a result, the local bias generator may control the body bias signal provided by the local bias generator.

Type: Application

Filed: January 21, 2005

Publication date: July 27, 2006

Inventors: James Tschanz, Stephen Tang, Victor Zia, Badarinath Kommandur, Siva Narendra, Vivek De
Leakage current management

Publication number: 20060140041

Abstract: A thermal feedback loop controls leakage current during burn-in of a circuit.

Type: Application

Filed: December 28, 2004

Publication date: June 29, 2006

Inventors: Arman Vassighi, Ali Keshavarzi, Vivek De

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