Abstract: An apparatus for particle collection is provided. The apparatus includes a magnetic element configured to generate a tapered magnetic ion transport tunnel that collects particles from a local environment, a detector configured to perform one or more measurements of the collected particles, and ion optics configured to transport the collected particles to the detector.

Abstract: An apparatus for particle collection is provided. The apparatus includes a magnetic element configured to generate a tapered magnetic ion transport tunnel that collects particles from a local environment, a detector configured to perform one or more measurements of the collected particles, and ion optics configured to transport the collected particles to the detector.

Abstract: An apparatus for particle collection is provided. The apparatus includes a magnetic element configured to generate a tapered magnetic ion transport tunnel that collects particles from a local environment, a detector configured to perform one or more measurements of the collected particles, and ion optics configured to transport the collected particles to the detector.

Abstract: An apparatus for radiation shielding is provided. The apparatus includes a first housing element and a first plurality of magnetic elements arranged in a first array on the first housing element. The first array is configured to generate a first tapered magnetic field and, using the first tapered magnetic field, deflect incoming radiation away from a protected element.

Abstract: An apparatus for particle collection is provided. The apparatus includes a magnetic element configured to generate a tapered magnetic ion transport tunnel that collects particles from a local environment, a detector configured to perform one or more measurements of the collected particles, and ion optics configured to transport the collected particles to the detector.

Abstract: Examples described in this disclosure relate to superconducting devices, including reciprocal quantum logic (RQL) compatible devices. A superconducting device including at least one superconducting element having a first coefficient of thermal expansion is provided. The at least one superconducting element is formed on a dielectric layer having a second coefficient of thermal expansion and the first coefficient of thermal expansion is different from the second coefficient of thermal expansion causing a strain mismatch between the at least one superconducting element and the dielectric layer when the superconducting device is operating in a cryogenic environment. The superconducting device may also include at least one dummy element configured to lower stress at an interface between the at least one superconducting element and the dielectric layer when the at least one superconducting device is operating in the cryogenic environment.

Abstract: Examples described in this disclosure relate to superconducting devices, including reciprocal quantum logic (RQL) compatible devices. A superconducting device including at least one superconducting element having a first coefficient of thermal expansion is provided. The at least one superconducting element is formed on a dielectric layer having a second coefficient of thermal expansion and the first coefficient of thermal expansion is different from the second coefficient of thermal expansion causing a strain mismatch between the at least one superconducting element and the dielectric layer when the superconducting device is operating in a cryogenic environment. The superconducting device may also include at least one dummy element configured to lower stress at an interface between the at least one superconducting element and the dielectric layer when the at least one superconducting device is operating in the cryogenic environment.

Abstract: A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.

Abstract: A semiconductor device includes a recess defined in a dielectric layer, the recess having an upper sidewall portion extending to an upper corner of the recess and a lower sidewall portion below the upper sidewall portion. An interconnect structure is positioned in the recess. The interconnect structure includes a continuous liner layer having upper and lower layer portions positioned laterally adjacent to the upper and lower sidewall portions, respectively. The upper layer portion includes an alloy of a first transition metal and a second transition metal and the lower layer portion includes the second transition metal but not the first transition metal. The interconnect structure also includes a fill material substantially filling the recess, wherein the second transition metal has a higher wettability for the fill material than the alloy.

Abstract: A semiconductor device includes a recess defined in a dielectric layer and an interconnect structure defined in the recess. The interconnect structure includes a first barrier layer lining the recess, the first barrier layer including an alloy of tantalum and a first transition metal other than tantalum, wherein a first interface between the first barrier layer and the dielectric layer has a first stress level. A second barrier layer is positioned on the first barrier layer, the second barrier layer including at least one of tantalum and tantalum nitride, wherein a second interface between the second barrier layer and the first barrier layer has a second stress level that is less than the first stress level. The interconnect structure further includes a fill material substantially filling the recess.

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a non-continuous layer comprised of a plurality of spaced-apart conductive structures on the layer of insulating material in the trench/via, wherein portions of the layer of insulating material not covered by the plurality of spaced-apart conductive structures remain exposed, forming at least one barrier layer on the non-continuous layer, wherein the barrier layer contacts the spaced-apart conductive structures and the exposed portions of the layer of insulating material, forming at least one liner layer above the barrier layer, and forming a conductive structure in the trench/via above the liner layer.

Abstract: Generally, the subject matter herein relates to detecting the presence of weak BEOL sites in a metallization system. One disclosed method includes performing a lateral force test on a pillar bump formed above a metallization system of a semiconductor chip, which includes contacting the pillar bump with a test probe while moving the test probe at a substantially constant speed that is less than approximately 1 ?m/sec along a path that is oriented at a substantially non-zero angle relative to a plane of the metallization system. Furthermore, the test probe is moving substantially away from the metallization system so that a force imposed on the pillar bump by the test probe has an upward component that induces a tensile load on the metallization system. The disclosed method also includes determining a behavioral interaction between the pillar bump and the metallization system during the lateral force test.

Abstract: Generally, the subject matter disclosed herein relates to testing pillar bumps formed on a semiconductor chip so as to detect the presence of anomalous stiff pillar bumps. One illustrative method disclosed herein includes positioning a test probe adjacent to a side of a pillar bump formed above a metallization system of a semiconductor chip, and performing a lateral force test on the pillar bump by contacting the side of the pillar bump with the test probe while moving the test probe at a substantially constant speed that is less than approximately 1 ?m/sec.

Abstract: A semiconductor chip includes at least one integrated circuit device and a bond pad that is electrically connected to the at least one integrated circuit device. The bond pad has an irregular configuration when viewed from above that corresponds to a first area portion that is defined by a first substantially regular geometric shape when viewed from above and a second area portion adjacent to the first area portion. The second area portion is located at a greater distance from a centerline of the semiconductor chip than any part of the first area portion when viewed from above, and two sides of the first area portion are substantially aligned with and substantially flush with two respective sides of the second area portion.

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier system comprised of at least one barrier material and at least two metallic elements, and performing a heating process to form a metal alloy comprised of the at least two metallic elements in the barrier system. Also disclosed is a device that comprises a trench/via in a layer of insulating material, a barrier system positioned in the trench/via, wherein the barrier system comprises at least one barrier material and a metal alloy comprised of at least two metallic elements that are comprised of materials other than the at least one barrier material, and a conductive structure positioned in the trench/via above the barrier system.

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier system comprised of at least one barrier material and at least two metallic elements, and performing a heating process to form a metal alloy comprised of the at least two metallic elements in the barrier system. Also disclosed is a device that comprises a trench/via in a layer of insulating material, a barrier system positioned in the trench/via, wherein the barrier system comprises at least one barrier material and a metal alloy comprised of at least two metallic elements that are comprised of materials other than the at least one barrier material, and a conductive structure positioned in the trench/via above the barrier system.

Abstract: A semiconductor device includes a recess defined in a dielectric layer and an interconnect structure defined in the recess. The interconnect structure includes a first barrier layer lining the recess, the first barrier layer including an alloy of tantalum and a first transition metal other than tantalum, wherein a first interface between the first barrier layer and the dielectric layer has a first stress level. A second barrier layer is positioned on the first barrier layer, the second barrier layer including at least one of tantalum and tantalum nitride, wherein a second interface between the second barrier layer and the first barrier layer has a second stress level that is less than the first stress level. The interconnect structure further includes a fill material substantially filling the recess.

Abstract: A system for repairing pillar bumps includes a pillar bump repair device that is adapted to form a plurality of strain-relieving notches in a pillar bump that is positioned above a metallization system of a semiconductor chip. The system further includes a pillar bump support device that is adapted to substantially support the pillar bump while the pillar bump repair device is forming each of the plurality of strain-relieving notches.

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a non-continuous layer comprised of a plurality of spaced-apart conductive structures on the layer of insulating material in the trench/via, wherein portions of the layer of insulating material not covered by the plurality of spaced-apart conductive structures remain exposed, forming at least one barrier layer on the non-continuous layer, wherein the barrier layer contacts the spaced-apart conductive structures and the exposed portions of the layer of insulating material, forming at least one liner layer above the barrier layer, and forming a conductive structure in the trench/via above the liner layer.

Abstract: A semiconductor device includes a dielectric layer positioned above a substrate of the semiconductor device and a recess defined in the dielectric layer. An adhesion barrier layer is positioned on and in direct contact with at least the sidewalls of the recess, a barrier layer interface being defined where the adhesion barrier layer directly contacts the dielectric layer. A stress-reducing barrier layer is positioned adjacent to the adhesion barrier layer, wherein the stress-reducing barrier layer is adapted to reduce a stress level across the barrier layer interface from a first stress level to a second stress level that is less than the first stress level. At least one layer of a conductive fill material is positioned over the stress-reducing barrier layer, the at least one layer of the conductive fill material substantially filling the recess.