Patents by Inventor Vivian W. Ryan

Vivian W. Ryan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020137330
    Abstract: A method for manufacturing integrated circuits; particularly, a method for fabricating a copper interconnect system and a copper interconnect system, having a layer of CrO, fabricated by the method.
    Type: Application
    Filed: April 11, 2002
    Publication date: September 26, 2002
    Inventor: Vivian W. Ryan
  • Patent number: 6410435
    Abstract: A method for manufacturing integrated circuits; particularly, a method for fabricating a copper interconnect system and a copper interconnect system, having a layer of CrO, fabricated by the method.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: June 25, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventor: Vivian W. Ryan
  • Patent number: 5930587
    Abstract: A method for accurately and objectively evaluating stress migration effects on long term reliability of integrated circuits. A sample containing a conductive runner is fabricated according to a given fabrication process. The fabricated sample undergoes a heating step at a first temperature for a first time period to induce material interactions at an accelerated rate, followed by cooling the sample to a second temperature and maintaining the second temperature for a time of sufficient duration such that relaxation occurs. Then the sample undergoes a heating process at a third temperature for a time sufficient to nucleate a predetermined number of voids, followed by heating the sample runner at a fourth temperature, less than than the third temperature, to propagate the voids such that a maximum void size is determined. Void distribution is preferably monitored by optical and scanning electron microscopy.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: July 27, 1999
    Assignee: Lucent Technologies
    Inventor: Vivian W. Ryan
  • Patent number: 5599737
    Abstract: The method of forming runners having superior stress migration characteristics is disclosed. A blanket layer of conductive material is deposited over a dielectric. A blanket layer is subjected to a blanket-etch back procedure, thereby reducing its thickness by approximately half. The remaining layer is then patterned to form runners. Resulting runners have a superior grain structure and greater resistance to electromigration and stress migration.
    Type: Grant
    Filed: December 30, 1994
    Date of Patent: February 4, 1997
    Assignee: Lucent Technologies Inc.
    Inventor: Vivian W. Ryan
  • Patent number: 5243221
    Abstract: Stress induced grain boundary movement in aluminum lines used as connections in integrated circuits is substantially avoided by doping the aluminum with iron. Through this expedient not only is grain boundary movement avoided but electromigration problems are also decreased.
    Type: Grant
    Filed: January 5, 1993
    Date of Patent: September 7, 1993
    Assignee: AT&T Bell Laboratories
    Inventors: Vivian W. Ryan, Ronald J. Schutz
  • Patent number: 4975389
    Abstract: Stress induced grain boundary movement in aluminum lines used as connections in integrated circuits is substantially avoided by doping the aluminum with iron. Through this expedient not only is grain boundary movemenmt avoided but electromigration problems are also decreased.
    Type: Grant
    Filed: October 25, 1989
    Date of Patent: December 4, 1990
    Assignee: AT&T Bell Laboratories
    Inventors: Vivian W. Ryan, Ronald J. Schutz
  • Patent number: 4826709
    Abstract: A sol-gel process is utilized for producing silicon oxide glasses useful in the manufacture of devices such as semiconductor devices. These glasses are easily deposited by techniques such as spinning. Not only is the glass easily applied, but also has advantageous electrical, etching, and mechanical properties. Thus, these glasses are useful in applications such as passivating layers for integrated circuit devices and as intermediary layers in trilevel lithography for the production of such devices.
    Type: Grant
    Filed: February 29, 1988
    Date of Patent: May 2, 1989
    Assignee: American Telephone and Telegraph Company AT&T Bell Laboratories
    Inventors: Vivian W. Ryan, Gerald Smolinsky