Patents by Inventor Vladimir Odnoblyudov

Vladimir Odnoblyudov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Solid-state transducer devices with selective wavelength reflectors and associated systems and methods
    Patent number: 10879428
    Abstract: Solid state transducer (“SST”) devices with selective wavelength reflectors and associated systems and methods are disclosed herein. In several embodiments, for example, an SST device can include a first emitter configured to emit emissions having a first wavelength and a second emitter configured to emit emissions having a second wavelength different from the first wavelength. The first and second emitters can be SST structures and/or converter materials. The SST device can further include a selective wavelength reflector between the first and second emitters. The selective wavelength reflector can be configured to at least substantially transmit emissions having the first wavelength and at least substantially reflect emissions having the second wavelength.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Martin F. Schubert, Vladimir Odnoblyudov
  • Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated systems and methods
    Patent number: 10879444
    Abstract: Solid-state transducers (“SSTs”) and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. The SST can further include a plurality of first contacts at the first side and electrically coupled to the first semiconductor material, and a plurality of second contacts extending from the first side to the second semiconductor material and electrically coupled to the second semiconductor material. An interconnect can be formed between at least one first contact and one second contact. The interconnects can be covered with a plurality of package materials.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Odnoblyudov, Martin F. Schubert
  • Ultrathin solid state dies and methods of manufacturing the same
    Patent number: 10840410
    Abstract: Various embodiments of SST dies and solid state lighting (“SSL”) devices with SST dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a SST die includes a substrate material, a first semiconductor material and a second semiconductor material on the substrate material, an active region between the first semiconductor material and the second semiconductor material, and a support structure defined by the substrate material. In some embodiments, the support structure has an opening that is vertically aligned with the active region.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Odnoblyudov, Martin F. Schubert
  • Gallium nitride epitaxial structures for power devices
    Patent number: 10833186
    Abstract: A method for making a multilayered device on an engineered substrate having a substrate coefficient of thermal expansion includes growing a buffer layer on the engineered substrate, and growing a first epitaxial layer on the buffer layer. The first epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: November 10, 2020
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Steve Lester, Ozgur Aktas
  • METHODS OF MANUFACTURING ENGINEERED SUBSTRATE STRUCTURES FOR POWER AND RF APPLICATIONS
    Publication number: 20200350154
    Abstract: A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial layers by epitaxial growth on the epitaxial silicon layer.
    Type: Application
    Filed: July 16, 2020
    Publication date: November 5, 2020
    Applicant: QROMIS, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens
  • GALLIUM-NITRIDE BASED DEVICES IMPLEMENTING AN ENGINEERED SUBSTRATE STRUCTURE
    Publication number: 20200335418
    Abstract: An electronic device includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a conductive layer coupled to the first adhesion layer, a second adhesion layer coupled to the conductive layer, and a barrier layer coupled to the second adhesion layer. The electronic device also includes a buffer layer coupled to the support structure, a contact layer coupled to the buffer layer, and a field-effect transistor (FET) coupled to the contact layer.
    Type: Application
    Filed: June 26, 2020
    Publication date: October 22, 2020
    Applicant: QROMIS, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens, Ozgur Aktas
  • Chip-on-board design with color mixing
    Patent number: 10811397
    Abstract: Some embodiments of the disclosure provide for a lighting system including a substrate. The lighting system includes several blue light emitting diodes (LEDs) supported by the substrate. The lighting system includes at least one red LED supported by the substrate. The lighting system includes a light conversion material covering the blue LEDs and the at least one red LED.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: October 20, 2020
    Assignee: BRIDGELUX INC.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Peng Chen
  • Wide band gap device integrated circuit architecture on engineered substrate
    Patent number: 10763299
    Abstract: A method includes forming a wide band gap (WBG) epitaxial layer on an engineered substrate. The WBG epitaxial layer includes a plurality of groups of epitaxial layers. The engineered substrate includes engineered layers formed on a bulk material having a coefficient of thermal expansion (CTE) matching a CTE of the WBG epitaxial layer. The method also includes forming a plurality of WBG devices based on the plurality of groups of epitaxial layers by: for each respective WBG device, forming internal interconnects and electrodes within a respective group of epitaxial layers. The method further includes forming external interconnects between the electrodes of different WBG devices of the plurality of WBG devices to form an integrated circuit.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: September 1, 2020
    Assignee: QROMIS, INC.
    Inventors: Vladimir Odnoblyudov, Cem Basceri
  • Methods of manufacturing engineered substrate structures for power and RF applications
    Patent number: 10763109
    Abstract: A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial III-V layers by epitaxial growth on the epitaxial silicon layer.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: September 1, 2020
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens
  • Method and system for forming doped regions by diffusion gallium nitride materials
    Patent number: 10763110
    Abstract: A method of forming doped regions by diffusion in gallium nitride materials includes providing a substrate structure including a gallium nitride layer and forming a mask on the gallium nitride layer. The mask exposes one or more portions of a top surface of the gallium nitride layer. The method also includes depositing a magnesium-containing gallium nitride layer on the one or more portions of the top surface of the gallium nitride layer and concurrently with depositing the magnesium-containing gallium nitride layer, forming one or more magnesium-doped regions in the gallium nitride layer by diffusing magnesium into the gallium nitride layer through the one or more portions. The magnesium-containing gallium nitride layer provides a source of magnesium dopants. The method further includes removing the magnesium-containing gallium nitride layer and removing the mask.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: September 1, 2020
    Assignee: QROMIS, INC.
    Inventors: Ozgur Aktas, Vladimir Odnoblyudov, Cem Basceri
  • Aluminum nitride based Silicon-on-Insulator substrate structure
    Patent number: 10755986
    Abstract: A substrate structure includes a polycrystalline substrate, a plurality of thin film layers disposed on the polycrystalline substrate, a bonding layer coupled to at least a portion of the plurality of thin films, and a single crystal silicon layer joined to the bonding layer.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: August 25, 2020
    Assignee: QROMIS, INC.
    Inventors: Ozgur Aktas, Vladimir Odnoblyudov, Dilip Risbud, Cem Basceri
  • MULTI-DEPOSITION PROCESS FOR HIGH QUALITY GALLIUM NITRIDE DEVICE MANUFACTURING
    Publication number: 20200258741
    Abstract: A group III-nitride (III-N)-based electronic device includes an engineered substrate, a metalorganic chemical vapor deposition (MOCVD) III-N-based epitaxial layer coupled to the engineered substrate, and a hybrid vapor phase epitaxy (HVPE) III-N-based epitaxial layer coupled to the MOCVD epitaxial layer.
    Type: Application
    Filed: April 29, 2020
    Publication date: August 13, 2020
    Applicant: QROMIS, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri
  • ULTRATHIN SOLID STATE DIES AND METHODS OF MANUFACTURING THE SAME
    Publication number: 20200251615
    Abstract: Various embodiments of SST dies and solid state lighting (“SSL”) devices with SST dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a SST die includes a substrate material, a first semiconductor material and a second semiconductor material on the substrate material, an active region between the first semiconductor material and the second semiconductor material, and a support structure defined by the substrate material. In some embodiments, the support structure has an opening that is vertically aligned with the active region.
    Type: Application
    Filed: February 28, 2020
    Publication date: August 6, 2020
    Inventors: Vladimir Odnoblyudov, Martin F. Schubert
  • Lateral high electron mobility transistor with integrated clamp diode
    Patent number: 10734486
    Abstract: A method of forming a semiconductor device includes providing an engineered substrate, forming a gallium nitride layer coupled to the engineered substrate, forming a channel region coupled to the gallium nitride layer by forming an aluminum gallium nitride barrier layer on the front surface of the gallium nitride layer, forming a gate dielectric layer coupled to the aluminum gallium nitride barrier layer in the central portion of the channel region, forming a gate contact coupled to the gate dielectric layer, forming a source contact at the first end of the channel region, forming a via at the second end of the channel region, filling the via with a conductive material, forming a drain contact coupled to the via, removing the engineered substrate to expose the back surface of the epitaxial gallium nitride layer, and forming a drain pad on the back surface of the epitaxial gallium nitride layer.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: August 4, 2020
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Ozgur Aktas
  • Power and RF devices implemented using an engineered substrate structure
    Patent number: 10734303
    Abstract: An electronic device includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a conductive layer coupled to the first adhesion layer, a second adhesion layer coupled to the conductive layer, and a barrier layer coupled to the second adhesion layer. The electronic device also includes a buffer layer coupled to the support structure, a contact layer coupled to the buffer layer, and a field-effect transistor (FET) coupled to the contact layer.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: August 4, 2020
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens, Ozgur Aktas
  • POLYCRYSTALLINE CERAMIC SUBSTRATE AND METHOD OF MANUFACTURE
    Publication number: 20200234945
    Abstract: A method of fabricating a ceramic substrate structure includes providing a ceramic substrate, encapsulating the ceramic substrate in a barrier layer, and forming a bonding layer coupled to the barrier layer. The method further includes removing a portion of the bonding layer to expose at least a portion of the barrier layer and define fill regions, and depositing a second bonding layer on the at least a portion of the exposed barrier layer and the fill regions.
    Type: Application
    Filed: January 27, 2020
    Publication date: July 23, 2020
    Applicant: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens
  • ENGINEERED SUBSTRATE STRUCTURES FOR POWER AND RF APPLICATIONS
    Publication number: 20200227251
    Abstract: A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial III-V layers by epitaxial growth on the epitaxial silicon layer.
    Type: Application
    Filed: April 1, 2020
    Publication date: July 16, 2020
    Applicant: QROMIS, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens
  • Linear LED module
    Patent number: 10711957
    Abstract: Various aspects of a light emitting apparatus include a substrate having at least one angled portion. Some aspects of the light emitting apparatus include at least one light emitting device arranged on the substrate. Some aspects of the light emitting apparatus include a plurality of conductors arranged on the substrate. In some aspects of the light emitting apparatus, the conductors are electrically coupled to the at least one light emitting device.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: July 14, 2020
    Assignee: BRIDGELUX INC.
    Inventor: Vladimir Odnoblyudov
  • RF DEVICE INTEGRATED ON AN ENGINEERED SUBSTRATE
    Publication number: 20200212213
    Abstract: A substrate for RF devices includes a polycrystalline ceramic core and an interlayer structure. The interlayer structure includes a first silicon oxide layer coupled to the polycrystalline ceramic core, a polysilicon layer coupled to the first silicon oxide layer, a second silicon oxide layer coupled to the polysilicon layer, a barrier layer coupled to the second silicon oxide layer, a third silicon oxide layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the third silicon oxide layer.
    Type: Application
    Filed: March 6, 2020
    Publication date: July 2, 2020
    Applicant: QROMIS, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Ozgur Aktas
  • RF DEVICE INTEGRATED ON AN ENGINEERED SUBSTRATE
    Publication number: 20200212214
    Abstract: A substrate for RF devices includes a polycrystalline ceramic core and an interlayer structure. The interlayer structure includes a first silicon oxide layer coupled to the polycrystalline ceramic core, a polysilicon layer coupled to the first silicon oxide layer, a second silicon oxide layer coupled to the polysilicon layer, a barrier layer coupled to the second silicon oxide layer, a third silicon oxide layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the third silicon oxide layer.
    Type: Application
    Filed: March 6, 2020
    Publication date: July 2, 2020
    Applicant: QROMIS, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Ozgur Aktas