Abstract: A computer implemented method for calculating a ground capacitance adjust for a wire segment going through a given routing tile. The method includes providing the routing tile having a plurality of wires wherein the wire segment being a victim wire and neighboring wires being aggressor wires; computing ground capacitance adjusts for a victim wire averaged across all aggressor slew values and across possible spacing values between the victim wire and the neighboring aggressor wires to take into account a potential coupling effect by the neighboring aggressor wires, assuming a distribution of signal slews of wires belonging to the routing tile and assuming the victim wire's neighbors have signal slews from the distribution of slews for this tile for possible spacing values responsible for the coupling effect, to guide placement of the wire segment in the routing tile to avoid coupling noise.

Abstract: Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In one example according to aspects of the present disclosure, a computer-implemented method is provided. The method comprises performing an initial statistical static timing analysis of the integrated circuit to create a parameterized model of the integrated circuit for a plurality of paths using a plurality of timing corners to calculate a timing value for each of the plurality of paths, each of the plurality of timing corners representing a set of timing performance parameters. The method further comprises determining at least one worst timing corner from the parameterized model for each of the plurality of paths based on the initial statistical static timing analysis and calculated timing value for each of the plurality of paths. The method also comprises performing a subsequent analysis of the integrated circuit using the at least one worst timing corner.

Abstract: A method, system, and computer program product to perform parallel multi-threaded common path pessimism removal in integrated circuit design include constructing, using a processor, a thread-specific graphical representation (TSGR) relating to each data node and clock node pair and performing processes in parallel for each TSGR. The processes include determining initial arrival times at the data node and the clock node, computing initial test slack based on the initial arrival times at the data node and the clock node, identifying fan-out nodes among the additional nodes, each fan-out node being an origin of at least two of the edges in the two or more paths to the clock node, generating one or more tags based the fan-out nodes, determining adjusted arrival times based on the one or more tags, and computing adjusted test slack based on the adjusted arrival times.

Abstract: A computer-implemented method includes identifying a noise cluster, representing the noise cluster according to a variational model, projecting the variational model onto one or more corners to yield a projected noise cluster, and determining a computed noise for the projected noise cluster. Optionally, the noise cluster includes one or more noise cluster elements, and each of the noise cluster elements are expressed as one or more circuit element terms, according to a canonical form. Optionally, at least one of the corners is a bounding corner. For the bounding corner, the projected noise cluster is generated by maximizing the circuit element terms for those noise cluster elements that tend to increase noise, and by minimizing the circuit element terms for those noise cluster elements that tend to decrease noise, whereby noise is maximized for the canonical form. A corresponding computer program product and computer system are also disclosed.

Abstract: A method of performing variation aware timing analysis for an integrated circuit, a system, and a computer program product are described. The method includes determining one or more voltage waveforms at an output of a first component of the integrated circuit based on respective one or more first processing conditions, and storing waveform information based on the one or more voltage waveforms. The method also includes obtaining an input voltage waveform at an input of a second component of the integrated circuit for a second processing condition based on processing the waveform information, the output of the first component being the input of the second component, and performing the variation aware timing analysis for the second component based on the input voltage waveform.

Abstract: A first plurality of relational tables is obtained from a relational database. Each table of the first plurality of relational tables stores connectivity information for a graph that comprises a plurality of nodes and a plurality of edges connecting the nodes, and each of the nodes is assigned an initial identifier. The nodes are clustered into a plurality of clusters. Each cluster contains a subset of the nodes, and all nodes in each subset are close to each other according to a metric. Each node is assigned a new identifier. The new identifier comprises a concatenation of an identifier associated with the cluster to which the node belongs and an identifier associated with the node. A second plurality of relational tables is constructed and stores connectivity information for the graph. The node is identified in the second plurality of relational tables by the new identifier.

Abstract: Improving automated timing analysis includes: generating a directed acyclic graph for an input netlist, generating a second order graph distance metric based at least on the directed acyclic graph, and scheduling a timing calculation for a set of nodes of the input netlist based at least on the second order graph distance metric.

Abstract: Improving automated timing analysis includes: generating a directed acyclic graph for an input netlist, generating a second order graph distance metric based at least on the directed acyclic graph, and scheduling a timing calculation for a set of nodes of the input netlist based at least on the second order graph distance metric.

Abstract: Methods for improving matrix multiplication runtimes are provided. A method includes determining, by a GPU, optimal partitions for matrix-by-matrix multiplication of two factor matrices having sizes known a priori. The determining step includes performing offline a plurality of matrix-by-matrix multiplication executions, each for a respective different combination of two-way partitions across a plurality of partition sizes. The determining step further includes determining offline a respective performance number for each of the executions based on runtime. The determining step also includes recursively repeating offline said performing and determining steps until the respective performance number ceases to improve for best-performing combinations of the two-way partitions and saving the best performing combinations of the two-way partitions as the optimal partitions.

Abstract: Methods and systems receive an integrated circuit design into a computerized device and perform an analysis of the integrated circuit design to identify characteristics of physical features of portions of the integrated circuit design. Such methods and systems determine whether to look up sensitivity of a timing value of a portion of the integrated circuit design to manufacturing process variables, voltage variables, and temperature variables (PVT variables) by: evaluating relationships between the characteristics of physical features of the portion of the integrated circuit design to generate an indicator value; and, based on whether the indicator value is within a table usage filter value range, either: calculating the sensitivity of the timing value to the PVT variables; or looking up a previously determined sensitivity of the timing value to the PVT variables from a look-up table.

Abstract: Methods and systems receive an integrated circuit design into a computerized device and perform an analysis of the integrated circuit design to identify characteristics of physical features of portions of the integrated circuit design. Such methods and systems determine whether to look up sensitivity of a timing value of a portion of the integrated circuit design to manufacturing process variables, voltage variables, and temperature variables (PVT variables) by: evaluating relationships between the characteristics of physical features of the portion of the integrated circuit design to generate an indicator value; and, based on whether the indicator value is within a table usage filter value range, either: calculating the sensitivity of the timing value to the PVT variables; or looking up a previously determined sensitivity of the timing value to the PVT variables from a look-up table.

Abstract: Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In one example according to aspects of the present disclosure, a computer-implemented method is provided. The method comprises performing an initial statistical static timing analysis of the integrated circuit to create a parameterized model of the integrated circuit for a plurality of paths using a plurality of timing corners to calculate a timing value for each of the plurality of paths, each of the plurality of timing corners representing a set of timing performance parameters. The method further comprises determining at least one worst timing corner from the parameterized model for each of the plurality of paths based on the initial statistical static timing analysis and calculated timing value for each of the plurality of paths. The method also comprises performing a subsequent analysis of the integrated circuit using the at least one worst timing corner.

Abstract: A method, system, and computer program product to perform dynamic voltage frequency scaling of an integrated circuit include performing statistical timing analysis using a canonical form of a clock, the canonical form of the clock being a function of variability in voltage. Obtaining a canonical model expressing timing slack at each test location of the integrated circuit is as a function of one or more sources of variability, one of the one or more sources of variability being voltage, and performing the dynamic voltage-frequency scaling based on selecting at least one of a clock period and the voltage using the canonical model.

Abstract: Statistically modeling timing in a digital circuit through the use of canonical form models, where some terms of the form represent sources of variation sensitive to only a subset of timing regions of the circuit. When propagating the form through regions through which some set of terms in the model is not sensitive, those terms are collapsed by placing them in a cache and replacing them in the form with a single combined term that references the cached terms.

Abstract: Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.

Abstract: Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to assign a color to each pattern shape in a first cell, assign a color to each pattern shape in a second cell, characterize quantities of interest for each pattern shape in the first cell, determine that the colors assigned in the first cell are all one to one mappable to the colors assigned in the second cells, characterize quantities of interest for each pattern shape in the second cell using the quantities of interest characterized for the first cell, and model the quantities of interest for the first cell and the second cell.

Abstract: A method includes forming a mixed integer linear problem (MILP) capturing at least a plurality of timing windows over which aggressor net(s), electromagnetically coupled to a victim net in a circuit, produce computed cross-talk noise pulses potentially contributing to a maximum noise for the victim net. The MILP is solved to determine the maximum noise at the victim net. Responsive to the maximum noise meeting one or more criteria, at least an indication of the victim net is output. Forming may include forming a linear problem using overlapping timing windows for which noise pulses contribute to the maximum noise and converting the linear problem to the mixed integer linear problem by introducing into the linear problem binary variables that determine whether individual ones of overlapping or non-overlapping noise pulses from the one or more aggressor nets contribute to the maximum noise. Apparatus and program products are also disclosed.

Abstract: Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation.

Abstract: A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-transitory storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.

Abstract: Systems and methods for improving timing closure of new and existing IC chips by breaking at least one parameter of interest into two or more partial parameters. More specifically, a method is provided for that includes propagating at least one timing analysis run for a semiconductor product. The method further includes identifying at least one parameter of interest used in the at least one timing analysis run. The method further includes splitting the at least one parameter into two parts comprising a controlled part and an uncontrolled part. The method further includes correlating or anti-correlating the controlled part with another parameter used in the at least one timing analysis run. The method further includes projecting timing using the correlation or anti-correlation between the controlled part and the another parameter and using the uncontrolled part of the at least one parameter.