Patents by Inventor Vladimir Zubkov
Vladimir Zubkov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070153282Abstract: The invention relates to analytical instrument engineering, in particular to spectroscopy. The inventive method for measuring spectroscopic properties of bulk products consists in portionwisely supplying a sample in a measurement area. In order to fully fill said measurement area, several portions (at least two) are loaded and alternately placed substantially in different fields of the horizontal section of the measurement area in such a way that the uniformed distribution and the permanent density of the product in the area of measurement are provided. Afterwards, the spectroscopic properties of the sample are recorded in a standstill and the sample is removed from the area of measurement.Type: ApplicationFiled: November 18, 2004Publication date: July 5, 2007Inventors: Vladimir Zubkov, Vladimir Timofeev, Aleksandr Shamrai
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Publication number: 20060269693Abstract: High tensile stress in a deposited layer such as silicon nitride, may be achieved utilizing one or more techniques, employed alone or in combination. High tensile stress may be achieved by forming a silicon-containing layer on a surface by exposing the surface to a silicon-containing precursor gas in the absence of a plasma, forming silicon nitride by exposing said silicon-containing layer to a nitrogen-containing plasma, and then repeating these steps to increase a thickness of the silicon nitride created thereby. High tensile stress may also be achieved by exposing a surface to a silicon-containing precursor gas in a first nitrogen-containing plasma, treating the material with a second nitrogen-containing plasma, and then repeating these steps to increase a thickness of the silicon nitride formed thereby. In another embodiment, tensile film stress is enhanced by deposition with porogens that are liberated upon subsequent exposure to UV radiation or plasma treatment.Type: ApplicationFiled: April 7, 2006Publication date: November 30, 2006Applicant: Applied Materials, Inc.Inventors: Mihaela Balseanu, Michael Cox, Li-Qun Xia, Mei-Yee Shek, Jia Lee, Vladimir Zubkov, Tzu-Fang Huang, Rongping Wang, Isabelita Roflox, Hichem M'Saad
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Publication number: 20060269692Abstract: Compressive stress in a film of a semiconductor device may be controlled utilizing one or more techniques, employed alone or in combination. A first set of embodiments increase silicon nitride compressive stress by adding hydrogen to the deposition chemistry, and reduce defects in a device fabricated with a high compressive stress silicon nitride film formed in the presence of hydrogen gas. A silicon nitride film may comprise an initiation layer formed in the absence of a hydrogen gas flow, underlying a high stress nitride layer formed in the presence of a hydrogen gas flow. A silicon nitride film formed in accordance with an embodiment of the present invention may exhibit a compressive stress of 2.8 GPa or higher.Type: ApplicationFiled: April 5, 2006Publication date: November 30, 2006Applicant: Applied Materials, Inc. A Delaware corporationInventors: Mihaela Balseanu, Li-Qun Xia, Vladimir Zubkov, Mei-Yee Shek, Isabelita Roflox, Hichem M'Saad
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Patent number: 7132336Abstract: An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric region formed over a channel region. A doped region is formed between a top portion and a bottom portion of the dielectric region. This doped region includes a suitable electron affinity material. A gate electrode is connected with the top of the dielectric region. In some embodiments, suitable electron affinity materials are introduced into the doped region using implantation techniques. In another embodiment, the electron affinity material is introduced into the doped region using plasma treatment of the dielectric region and the redeposition of additional dielectric material on top of the dielectric region and doped region.Type: GrantFiled: April 15, 2002Date of Patent: November 7, 2006Assignee: LSI Logic CorporationInventors: Sheldon Aronowitz, Vladimir Zubkov, Grace S. Sun
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Patent number: 7115991Abstract: A barrier layer for a semiconductor device is provided. The semiconductor device comprises a dielectric layer, an electrically conductive copper containing layer, and a barrier layer separating the dielectric layer from the copper containing layer. The barrier layer comprises a silicon oxide layer and a dopant, where the dopant is a divalent ion, which dopes the silicon oxide layer adjacent to the copper containing layer. A method of forming a barrier layer is provided. A silicon oxide layer with a surface is provided. The surface of the silicon oxide layer is doped with a divalent ion to form a barrier layer extending to the surface of the silicon oxide layer. An electrically conductive copper containing layer is formed on the surface of the barrier layer, where the barrier layer prevents diffusion of copper into the substrate.Type: GrantFiled: October 22, 2001Date of Patent: October 3, 2006Assignee: LSI Logic CorporationInventors: Vladimir Zubkov, Sheldon Aronowitz
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Patent number: 7081296Abstract: A method of forming a layer over a substrate is provided. Generally, a layer of a first reactive species is deposited over the substrate. The layer of the first reactive species is reacted with a second reactive species to create a first product. Unreacted reactive species is preferentially desorbed leaving a layer of the first product.Type: GrantFiled: March 16, 2004Date of Patent: July 25, 2006Assignee: LSI Logic CorporationInventors: Sheldon Aronowitz, Vladimir Zubkov, Richard Schinella
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Patent number: 7015096Abstract: In one embodiment, bimetallic oxide compositions for gate dielectrics that include two or more of the elements Ca, Sr, Ba, Hf, and Zr are described.Type: GrantFiled: July 1, 2004Date of Patent: March 21, 2006Assignee: LSI Logic CorporationInventors: Vladimir Zubkov, Sey-Shing Sun
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Patent number: 7015168Abstract: The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes containing one or more organofluoro silanes having the formula SiR1R2R3R4, where: (a) R1 is selected from H, a 3 to 10 carbon alkyl, and an alkoxy; (b) R2 contains at least one C atom bonded to at least one F atom, and no aliphatic C—H bonds; and (c) R3 and R4 are selected from H, alkyl, alkoxy, a moiety containing at least one C atom bonded to at least one F atom, and ((L)Si(R5)(R6))n(R7); where n ranges from 1 to 10; L is O or CFR8; each n R5 and R6 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; R7 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; and each R8 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom.Type: GrantFiled: August 29, 2003Date of Patent: March 21, 2006Assignee: LSI Logic CorporationInventors: Sheldon Aronowitz, Vladimir Zubkov
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Patent number: 6998343Abstract: A method for forming damascene interconnect copper diffusion barrier layers includes implanting calcium into the sidewalls of the trenches and vias. The calcium implantation into dielectric layers, such as oxides, is used to prevent Cu diffusion into oxide, such as during an annealing process step. The improved barrier layers of the present invention help prevent delamination of the Cu from the dielectric.Type: GrantFiled: November 24, 2003Date of Patent: February 14, 2006Assignee: LSI Logic CorporationInventors: Grace Sun, Vladimir Zubkov, William K. Barth, Sethuraman Lakshminarayanan, Sey-Shing Sun, Agajan Suvkhanov, Hao Cui
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Patent number: 6989565Abstract: An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric stack formed over a channel region of a semiconductor substrate. The dielectric stack includes a layer of electron trapping material that operates as a charge storage center for memory devices. A gate electrode is connected with the top of the dielectric stack. In various embodiments the electron trapping material forms a greater or lesser portion of the dielectric stack. The invention includes a method embodiment for forming such a memory device.Type: GrantFiled: October 31, 2003Date of Patent: January 24, 2006Assignee: LSI Logic CorporationInventors: Sheldon Aronowitz, Vladimir Zubkov, Grace S. Sun
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Publication number: 20050258475Abstract: An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric stack formed over a channel region of a semiconductor substrate. The dielectric stack includes a layer of electron trapping material that operates as a charge storage center for memory devices. A gate electrode is connected with the top of the dielectric stack. In various embodiments the electron trapping material forms a greater or lesser portion of the dielectric stack. The invention includes a method embodiment for forming such a memory device.Type: ApplicationFiled: July 25, 2005Publication date: November 24, 2005Inventors: Sheldon Aronowitz, Vladimir Zubkov, Grace Sun
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Publication number: 20050179138Abstract: A barrier layer for a semiconductor device is provided. The semiconductor device comprises a dielectric layer, an electrically conductive copper containing layer, and a barrier layer separating the dielectric layer from the copper containing layer. The barrier layer comprises a silicon oxide layer and a dopant, where the dopant is a divalent ion, which dopes the silicon oxide layer adjacent to the copper containing layer. A method of forming a barrier layer is provided. A silicon oxide layer with a surface is provided. The surface of the silicon oxide layer is doped with a divalent ion to form a barrier layer extending to the surface of the silicon oxide layer. An electrically conductive copper containing layer is formed on the surface of the barrier layer, where the barrier layer prevents diffusion of copper into the substrate.Type: ApplicationFiled: April 12, 2005Publication date: August 18, 2005Inventors: Vladimir Zubkov, Sheldon Aronowitz
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Patent number: 6919263Abstract: A new relatively high-k gate dielectric gate material comprising calcium oxide will reduce leakage from the silicon substrate to the polysilicon gate, prevent boron penetration in p-channel devices, and reduce electron trapping in the dielectric. The surface of a silicon wafer is saturated with hydroxyl groups. A calcium halide, preferably calcium bromide, is heated to a temperature sufficient to achieve atomic layer deposition, and is transported to the silicon wafer. The calcium halide reacts with the hydroxyl groups. Water is added to carry away the resultant hydrogen halide. Gaseous calcium and water are then added to form a calcium oxide gate dielectric, until the desired thickness has been achieved. In an alternative embodiment of the method, the calcium halide is transported to the silicon wafer to react with the hydroxyl groups, followed by transport of gaseous water to the silicon wafer. These two steps are repeated until the desired thickness has been achieved.Type: GrantFiled: August 19, 2003Date of Patent: July 19, 2005Assignee: LSI Logic CorporationInventors: Sheldon Aronowitz, Vladimir Zubkov, Grace Sun
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Publication number: 20050098856Abstract: The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes containing one or more organofluoro silanes having the formula SiR1R2R3R4, where: (a) R1 is selected from H, a 3 to 10 carbon alkyl, and an alkoxy; (b) R2 contains at least one C atom bonded to at least one F atom, and no aliphatic C—H bonds; and (c) R3 and R4 are selected from H, alkyl, alkoxy, a moiety containing at least one C atom bonded to at least one F atom, and ((L)Si(R5)(R6))n(R7); where n ranges from 1 to 10; L is O or CFR8; each n R5 and R6 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; R7 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; and each R8 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom.Type: ApplicationFiled: August 29, 2003Publication date: May 12, 2005Inventors: Sheldon Aronowitz, Vladimir Zubkov
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Patent number: 6858195Abstract: The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes that include one or more organofluoro silanes selected from: (a) an organofluoro silane containing two silicon atoms linked by one oxygen atom; (b) an organofluoro silane containing two silicon atoms linked by one or more carbon atoms, where the one or more carbon atoms each are bonded to one or more fluorine atoms, or to one or more organofluoro moieties, or to a combination thereof; and (c) an organofluoro silane containing a silicon atom bonded to an oxygen atom. The invention also provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes that include one or more organofluoro silanes characterized by the presence of Si—O bonds.Type: GrantFiled: February 23, 2001Date of Patent: February 22, 2005Assignee: LSI Logic CorporationInventors: Sheldon Aronowitz, Vladimir Zubkov
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Patent number: 6822308Abstract: A method of chemically altering a silicon surface and associated dielectric materials are disclosed.Type: GrantFiled: June 20, 2003Date of Patent: November 23, 2004Assignee: LSI Logic CorporationInventors: Sheldon Aronowitz, Vladimir Zubkov
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Publication number: 20040175947Abstract: A method of forming a layer over a substrate is provided. Generally, a layer of a first reactive species is deposited over the substrate. The layer of the first reactive species is reacted with a second reactive species to create a first product. Unreacted reactive species is preferentially desorbed leaving a layer of the first product.Type: ApplicationFiled: March 16, 2004Publication date: September 9, 2004Applicant: LSI Logic CorporationInventors: Sheldon Aronowitz, Vladimir Zubkov, Richard Schinella
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Publication number: 20040121550Abstract: A method of creating a barrier to metal contamination in interconnect and gate oxides comprises ion implantation of an alkaline earth metal into the silicon dioxide. The presence of the implanted alkaline earth metal, preferably calcium, traps metal contaminants and thereby creates a barrier to further contamination. Alternatively, the alkaline earth metal can be implanted into the silicon dioxide as a low energy plasma. The implantation of atomic calcium into gate oxide serves to trap boron and thereby minimize boron diffusion from a polysilicon gate into silicon.Type: ApplicationFiled: December 19, 2002Publication date: June 24, 2004Inventors: Vladimir Zubkov, Grace Sun, Sheldon Aronowitz
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Patent number: 6747358Abstract: Embodiments of the invention include a capping layer of alloy material formed over a copper-containing layer, the alloy configured to prevent diffusion of copper through the capping layer. In another embodiment the alloy capping layer is self-aligned to the underlying conducting layer. Specific embodiments include capping layers formed of alloys of copper with materials including but not limited to calcium, strontium, barium, and other alkaline earth metals, as well as materials from other groups, for example, cadmium or selenium. The invention also includes methods for forming an alloy capping layer on a copper-containing conducting structure. One such method includes providing a substrate having formed thereon electrically conducting layer comprised of a copper-containing material and forming an alloy capping layer on the electrically conducting layer. In another method embodiment, forming the alloy capping layer includes forming a self-aligned capping layer over the conducting layer.Type: GrantFiled: February 18, 2003Date of Patent: June 8, 2004Assignee: LSI Logic CorporationInventors: Paul Rissman, Richard Schinella, Sheldon Aronowitz, Vladimir Zubkov
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Patent number: 6743474Abstract: A method of forming a layer over a substrate is provided. Generally, a layer of a first reactive species is deposited over the substrate. The layer of the first reactive species is reacted with a second reactive species to create a first product. Unreacted reactive species is preferentially desorbed leaving a layer of the first product.Type: GrantFiled: October 25, 2001Date of Patent: June 1, 2004Assignee: LSI Logic CorporationInventors: Sheldon Aronowitz, Vladimir Zubkov, Richard Schinella