Abstract: In multiple port chip circuit, an ESD protection circuit and method of protecting the ports of the multiple port circuit, includes providing a plurality of bi-directional snapback devices such as DIACs and connecting only one electrode to ground while connecting the other electrodes to the ports that are to be protected.

Abstract: A method is provided for forming a graded junction in a semiconductor material having a first conductivity type. Dopant having a second conductivity type opposite the first conductivity type is introduced into a selected region of the semiconductor material to define a primary dopant region therein. The perimeter of the primary dopant region defines a primary pn junction. While introducing dopant into the selected region of the semiconductor material, dopant is simultaneously introduced into the semiconductor material around the perimeter of the primary dopant region and spaced-apart from the primary pn junction. The dopant in the both the primary dopant region and in the dopant around the perimeter of the primary dopant region is then diffused to provide a graded dopant region.

Abstract: A power transistor structure uses metal drain and source strips with non-uniform widths to reduce variations in current density across the power transistor structure. The reductions in current density, in turn, reduce the source-to-drain turn on resistance and maximize the overall current carrying capacity of power transistor structure.

Abstract: In a method and structure for a high voltage LDMOS with reduced hot carrier degradation, the thick field oxide is eliminated and a reduced surface field achieved instead by including adjacent p+ and n+ regions in the drain well and shorting these regions to each other, or by including a p+ region in the drain well and biasing it to a positive voltage relative to the source voltage.

Abstract: A synchronous clock signal is generated in a large number of local clock circuits at the same time by exposing photoconductive regions in each local clock circuit to a pulsed light source that operates at a fixed frequency. The photoconductive regions generate photoconductive currents which are sufficient to cause a logic inverter to switch states.

Abstract: In a multiple input ESD protection structure, the inputs are isolated from the substrate by highly doped regions of opposite polarity to the input regions. Dual polarity is achieved by providing a symmetrical structure with n+ and p+ regions forming each dual polarity input. The inputs are formed in a p-well which, in turn, is formed in a n-well. Each dual polarity input is isolated by a PBL under the p-well, and a NISO underneath the n-well. An isolation ring separates and surrounds the inputs. The isolation ring comprises a p+ ring or a p+ region, n+ region, and p+ region formed into adjacent rings.

Abstract: An SCR device having a first P type region disposed in a semiconductor body and electrically connected to anode terminal of the device. At least one N type region is also disposed in the body adjacent the first P type region so as to form a PN junction having a width Wn near a surface of the semiconductor body. A further P type region is also disposed in the body to form a further PN junction with the N type region, with the junction having a width Wp near the body surface, with Wp being at least 1.5 times width Wn. A further N type region is provided which is electrically connected to a cathode terminal of the device and forming a third PN junction with the further N type region.

Abstract: The turn on time of an electrostatic discharge (ESD) structure, such as a silicon controlled rectifier (SCR), a low-voltage triggering SCR (LVTSCR), and a bipolar SCR (BSCR), is reduced by turning on the structure in two steps: a first step that locally turns on the pnp and npn transistors, and a second step that, over time, fully turns on the structure.

Abstract: An apparatus and method for a heat sink to dissipate the heat sourced by the encapsulated transistors in a SOI wafer. The apparatus includes a transistor formed in the active silicon layer of the wafer. The active surface is formed over an oxide layer and a bulk silicon layer. A heat sink is formed in the bulk silicon layer and configured to sink heat through the bulk silicon layer, to the back surface of the wafer. After the transistor is fabricated, the heat sink is formed by masking, patterning and etching the back surface of the wafer to form plugs in the bulk silicon layer. The plug extends through the thickness of the bulk layer to the oxide layer. Thereafter, the plug is filled with a thermally conductive material, such as a metal or DAG (thermally conductive paste). During operation, heat from the transistor is dissipated through the heat sink. In various embodiments of the invention, the plug hole is formed using either an anisotropic plasma or wet etch.

Abstract: In a triggering ESD protection structure, the triggering voltage is reduced by introducing one or more corners or spikes into the p-n breakdown junction. This may be done by providing a polygate with a zig-zag pattern to define triangular corners in the drain or anode of the structure.

Abstract: NVM cell for storing three levels of charge: one erased and two programmed states. The cell comprises a transistor structure providing a gate current versus gate voltage curve having a shape with a flat region or a second peak. To provide such a structure, one embodiment combines two parallel transistors having different threshold voltages, and another embodiment uses one transistor with variable doping. The gate current curve provides two programming zones. Programming the first state includes applying a voltage across a channel, ramping up a gate voltage in the first programming zone, followed by ramping it back down. Programming the second state comprises applying a voltage across a channel, ramping up a gate voltage past the first programming zone and into the second programming zone, followed by ramping it back down. Ramping the voltage back down may optionally be preceded by turning off the voltage across the channel.

Abstract: A single junction interdigitated photodiode utilizes a stack of alternating highly doped first regions of a first conductivity type and highly doped second regions of a second conductivity type, which are formed below and contact the first regions, to collect photons. In addition, a highly doped sinker of a first conductivity type contacts each first region, and a highly doped sinker of a second conductivity type contacts each second region.

Abstract: A linear time-driver circuit is provided that consumes low space on-chip. The time-driver circuit is based upon the small capacitor charge of the merged region of a 5V tolerant cascaded NMOS device, a single gate device and a zener diode.

Abstract: The linear tuning range of a semiconductor varactor is substantially increased by forming a lightly-doped drain region of a first conductivity type in a semiconductor material of a second conductivity type between a heavily-doped diffusion of the second conductivity type and a lower-plate region of the semiconductor material.

Abstract: An ESD protection structure includes a semiconductor substrate of a first conductivity type, and first and second well regions of a second conductivity type disposed in the substrate. The first and second well regions are separated by a gap region of the substrate. Also included are first and second floating regions (of the second conductivity type) disposed in the first and second well regions adjacent to the gap region, respectively. The ESD protection structure also includes first and second contact regions of the first conductivity type disposed on the first and second well regions, respectively, and spaced apart from the first and second floating regions, respectively. The ESD protection structure also includes first and second contact regions of the second conductivity type disposed on the first and second well regions, respectively, and spaced apart from the first and second floating regions, respectively.

Abstract: When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantially reduced by forming the collector of the NPN transistor between the emitter and collector of the PNP transistor.

Abstract: A photon detector capable of detecting gigahertz frequency optical signals utilizes a layer of photonic material that is formed adjacent to the coil of an inductor. When a pulsed light source is applied to the layer of photonic material, the photonic material generates eddy currents that alter the magnetic flux of the inductor. The signals can then be detected by detecting the change in the magnetic flux.

Abstract: Electrostatic discharge (ESD) protection clamp circuitry including current tunneling circuitry to provide control current for controlling current shunting circuitry for shunting ESD current from the protected signal terminal.

Abstract: In an ESD protection device making use of a LVTSCR-like structure or an IGBT-like structure, negative polarity over-voltage protection is achieved by providing a LVTSCR-like structure or IGBT-like structure that defines a PMOS device.

Abstract: In an avalanche structure, different breakdown voltages are achieved by making use of a polygate and forming a highly doped p-n junction beneath the polygate, and adjusting the gate length and optionally the bias voltage of the gate.