Abstract: A charge pump circuit in which at least one of the switching elements takes the form of a LVTSCR. The switching on and off of the LVTSCRs may be achieved by making use of a pulsed input and relying on the triggering and holding voltages of the LVTSCRs to switch on and off.

Abstract: In an integrated circuit, dopant concentration levels are adjusted by making use of a perforated mask. Doping levels for different regions across an integrated circuit can be differently defined by making use of varying size and spacings to the perforations in the mask. The diffusion of dopant is completed by making use of an annealing stage.

Abstract: A stacked high-voltage ESD protection clamp is provided that realizes the desired triggering characteristics of a BJT or BSCR stacked snapback clamp. The operational principle of the new circuit is based upon introduction of a middle node capacitor into the stacked (cascoded) clamp. The capacitor (or driver) provides conditions for a two-stage turn-on. At the beginning of an ESD pulse, the capacitor is discharged. With the ESD voltage increase, part of the current is used to charge the capacitor, thus shunting one of the BJTs (BSCRs). As a result, the other BJT (BSCR) will experience fast turn-on. After turn-on, the current provides a fast charge of the capacitor and the turn-on of the second device. Thus, the middle node capacitor allows the triggering characteristics of the clamp to be controlled.

Abstract: High voltage tolerant electrostatic discharge (ESD) protection clamp circuitry including a self-triggering device having a blocking junction with a two-dimensional geometrical lateral profile.

Abstract: Spin-based microelectronic devices can be realized by utilizing ferromagnetic structures that make good ohmic contact with silicon, in order to avoid the Schottky barrier problem plaguing existing approaches to spin-based microelectronics, while allowing the devices to be based on silicon substrates, which are well-known and used in the industry. Thin layers of metal silicide, such as CoSi2 and NiSi2, are used as an intermediate layer between ferromagnetic contacts, such as cobalt and nickel contacts, and the silicon substrate. The thin silicide layers provide good ohmic contact between the ferromagnetic contacts and silicon, such that spin-polarized carriers can be injected into the silicon, and detected out of the silicon, without loss of spin polarization.

Abstract: In an ESD protection device using a SCR-like structure, a vertical device is provided that is highly robust and easily allows the triggering voltage to be adjusted during manufacture. Furthermore it is implementable in complementary form based on PNP and NPN BJT structures, to provide both positive and negative pulse protection.

Abstract: A semiconductor die is formed in a process that forms a hole through the wafer prior to the formation of the contacts and the metal-1 layer of an interconnect structure. The through-the-wafer hole is formed by using a wafer with a <110> crystallographic orientation and a wet etch, such as with ethanol (KOH) or tetramethylammonium hydroxide (TMAH).

Abstract: The integration period of an imaging cell, or the time that an imaging cell is exposed to light energy, is substantially increased by utilizing a single-poly, electrically-programmable, read-only-memory (EPROM) structure to capture the light energy. Photogenerated electrons are formed in the channel region of the EPROM structure from the light energy. The photogenerated electrons are then accelerated into having ionizing collisions which, in turn, leads to electrons being injected onto the floating gate of the EPROM structure at a rate that is proportionate to the number of photons captured by the channel region.

Abstract: A method of programming a nonvolatile memory cell in which a ramped control voltage is used to obtain the desired voltage on the storage node.

Abstract: A programming technique for a one-time-programmable non-volatile memory (NVM) utilizes a repeated programming cycle with an interval between cycles that is long enough to redistribute charge in the layers surrounding the floating gate of the cell. Each cycle programs the floating gate and also the surrounding layers. The cycling saturates in an equilibrium state when the electric field form outside to the floating gate equals zero. This technique eliminates the first stage of conventional VT drop in NVM cells and, thus, improves retention.

Abstract: The image capture period of an imaging cell, or the total time that an imaging cell is exposed to light energy, is substantially increased by utilizing a non-volatile memory (NVM), such as an electrically-erasable, programmable, read-only-memory (EEPROM) structure. The NVM structure stores and integrates charges that are proportional to the absorbed photons over a large number of sequential integration periods.

Abstract: The integration period of an imaging cell, or the time that an imaging cell is exposed to light energy, is substantially increased by utilizing a single-poly, electrically-programmable, read-only-memory (EPROM) structure to capture the light energy. Photogenerated electrons are formed in the channel region of the EPROM structure from the light energy. The photogenerated electrons are then accelerated into having ionizing collisions which, in turn, leads to electrons being injected onto the floating gate of the EPROM structure at a rate that is proportionate to the number of photons captured by the channel region.

Abstract: In an SCR-based ESD protection clamp, the voltage overshoot during an ESD event is reduced by separately controlling the voltage pulse to the drain and emitter contacts of the SCR. The voltage pulse to the drain is preferably delayed using a delay circuit such as an RC circuit. This allows double conductivity modulation to be achieved with lower voltage overshoot.

Abstract: In a BJT, the extrinsic base to collector capacitance is reduced by forming a lateral trench between the extrinsic base region and collector. This is typically done by using an anisotropic wet etch process in a <110> direction of a <100> orientation wafer.

Abstract: Spin-based microelectronic devices can be realized by utilizing ferromagnetic structures that make good ohmic contact with silicon, in order to avoid the Schottky barrier problem plaguing existing approaches to spin-based microelectronics, while allowing the devices to be based on silicon substrates, which are well-known and used in the industry. Thin layers of metal silicide, such as CoSi2 and NiSi2, are used as an intermediate layer between ferromagnetic contacts, such as cobalt and nickel contacts, and the silicon substrate. The thin silicide layers provide good ohmic contact between the ferromagnetic contacts and silicon, such that spin-polarized carriers can be injected into the silicon, and detected out of the silicon, without loss of spin polarization.

Abstract: Spin-based microelectronic devices can be realized by utilizing spin-polarized ferromagnetic materials positioned near, or embedded in, a semiconductor channel of a microelectronic device. Applying an electric field across the channel can cause carriers flowing through the channel to deviate toward one of the ferromagnetic materials, such that the spin of the carriers tends to align with the spin polarization of the respective material. Such a process allows for the controlled spin-polarization of carriers in a semiconductor channel, and hence the development of spin-based microelectronics, without having to inject spin-polarized carriers from a ferromagnet into a semiconductor channel. Such a process avoids the Schottky barrier problem plaguing existing approaches to spin-based microelectronics, while allowing the devices to be based on silicon substrates that are well-known and used in the industry.

Abstract: In a self protection I/O, a multiple gate NMOS structure is designed to shift the avalanche multiplication region away from the edge of the gate nearest the drain. This is achieved by providing a lightly doped region between the edge of the gate and the ballast region of the drain.

Abstract: A method is provided for erasing a nonvolatile memory cell that includes a source region, a drain region, a floating gate electrode and a control gate electrode to which an erase signal is applied. In accordance with the method, a source bias voltage is applied to the source region, a drain bias voltage is applied to the drain region, and a frequency/time domain based voltage signal is applied to the control gate electrode of the cell as the erase signal.

Abstract: The holding voltage (the minimum voltage required for operation) of a LVTSCR-like device is increased to a value that is greater than a dc bias on a to-be-protected node. The holding voltage is increased by reducing the size of the p+ emitter defined by the LVTSCR-like device. As a result, the LVTSCR can be utilized to provide ESD protection to power supply pins, having better current capabilities than a GGNMOS and better holding voltage characteristics than a LVTSCR.

Abstract: An integrated circuit trim structure includes a dopant source, a target trim element formed in proximity to the dopant source, and a conductive heating element. The heater element is formed in proximity to the dopant source and includes first and second terminals and a trapezoid shaped region formed between the first and second terminals. As predefined current pulse is applied to the first terminal to promote current flow between the first and second terminals, a local heat source is created at a predefined location within the trapezoid shaped region and in proximity to the dopant source such that dopant flows from the dopant source into the target trim element to change the conductive characteristics of the target trim element.