Patents by Inventor Voon-Yew Thean

Voon-Yew Thean has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10340139
    Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, mask structure includes a first level defining a first trench extending through the first level, wherein a bottom of the first trench is defined by a semiconductor substrate, and a second level on top of the first level, wherein the second level defines a plurality of second trenches positioned at a non-zero angle with respect to the first trench.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: July 2, 2019
    Assignee: IMEC
    Inventors: Benjamin Vincent, Voon Yew Thean, Liesbeth Witters
  • Patent number: 10309925
    Abstract: The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices such as field-effect transistor devices configured for biomolecule sensing. In one aspect, a semiconductor chip comprises at least one field-effect transistor device which comprises a source, a drain, a gate stack and a channel region formed between the source and the drain. The gate stack only partially overlaps the channel region at the source side and/or at the drain side, such that a non-overlapped channel region at the source side and/or at the drain side is formed, where the non-overlapped channel region is configured for sensing biomolecules.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: June 4, 2019
    Assignee: IMEC vzw
    Inventors: Nadine Collaert, Voon Yew Thean
  • Patent number: 10211312
    Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a non-volatile ferroelectric memory device and to methods of fabricating the same. In one aspect, a non-volatile memory device includes a high dielectric constant layer (high-k) layer or a metal layer on a semiconductor substrate. The non-volatile memory device additionally includes a two-dimensional (2D) semiconductor channel layer interposed between the high-k layer or metal layer and a ferroelectric layer. The non-volatile memory device additionally includes a metal gate layer on the ferroelectric layer, and further includes a source region and a drain region each electrically coupled to the 2D semiconductor channel layer.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: February 19, 2019
    Assignee: IMEC vzw
    Inventors: Jan Van Houdt, Voon Yew Thean
  • Publication number: 20170040168
    Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, mask structure includes a first level defining a first trench extending through the first level, wherein a bottom of the first trench is defined by a semiconductor substrate, and a second level on top of the first level, wherein the second level defines a plurality of second trenches positioned at a non-zero angle with respect to the first trench.
    Type: Application
    Filed: October 25, 2016
    Publication date: February 9, 2017
    Applicant: IMEC
    Inventors: Benjamin Vincent, Voon Yew Thean, Liesbeth Witters
  • Publication number: 20170040331
    Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a non-volatile ferroelectric memory device and to methods of fabricating the same. In one aspect, a non-volatile memory device includes a high dielectric constant layer (high-k) layer or a metal layer on a semiconductor substrate. The non-volatile memory device additionally includes a two-dimensional (2D) semiconductor channel layer interposed between the high-k layer or metal layer and a ferroelectric layer. The non-volatile memory device additionally includes a metal gate layer on the ferroelectric layer, and further includes a source region and a drain region each electrically coupled to the 2D semiconductor channel layer.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 9, 2017
    Inventors: Jan Van Houdt, Voon Yew Thean
  • Publication number: 20160320336
    Abstract: The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices such as field-effect transistor devices configured for biomolecule sensing. In one aspect, a semiconductor chip comprises at least one field-effect transistor device which comprises a source, a drain, a gate stack and a channel region formed between the source and the drain. The gate stack only partially overlaps the channel region at the source side and/or at the drain side, such that a non-overlapped channel region at the source side and/or at the drain side is formed, where the non-overlapped channel region is configured for sensing biomolecules.
    Type: Application
    Filed: April 29, 2016
    Publication date: November 3, 2016
    Inventors: Nadine COLLAERT, Voon Yew Thean
  • Patent number: 9476143
    Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, the method may comprise providing a substrate comprising a first crystalline material, where the first crystalline material has a first lattice constant; providing a mask structure on the substrate, where the mask structure comprises a first level comprising a first opening extending through the first level (where a bottom of the first opening comprises the substrate), and a second level on top of the first level, where the second level comprises a plurality of second trenches positioned at a non-zero angle with respect to the first opening. The method may further comprise epitaxially growing a second crystalline material on the bottom of the first opening, where the second crystalline material has a second lattice constant different than the first lattice constant and defects in the second crystalline material are trapped in the first opening.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: October 25, 2016
    Assignee: IMEC
    Inventors: Benjamin Vincent, Voon Yew Thean, Liesbeth Witters
  • Patent number: 9368498
    Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: June 14, 2016
    Assignee: IMEC
    Inventors: Geert Eneman, Benjamin Vincent, Voon Yew Thean
  • Publication number: 20160027777
    Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.
    Type: Application
    Filed: October 8, 2015
    Publication date: January 28, 2016
    Applicant: IMEC VZW
    Inventors: Geert ENEMAN, Benjamin VINCENT, Voon Yew THEAN
  • Patent number: 9171904
    Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: October 27, 2015
    Assignee: IMEC
    Inventors: Geert Eneman, Benjamin Vincent, Voon Yew Thean
  • Publication number: 20140151766
    Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.
    Type: Application
    Filed: November 21, 2013
    Publication date: June 5, 2014
    Applicant: IMEC
    Inventors: Geert Eneman, Benjamin Vincent, Voon Yew Thean
  • Patent number: 8623714
    Abstract: The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: January 7, 2014
    Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing, Ltd., Samsung Electronics Co., Ltd.
    Inventors: Jae-Eun Park, Weipeng Li, Deleep R. Nair, M. Dean Sciacca, Voon-Yew Thean, Ava Wan, Dong-Hun Lee, Yong-Meng Lee
  • Patent number: 8587039
    Abstract: A semiconductor device is formed in a semiconductor layer. A gate stack is formed over the semiconductor layer and comprises a first conductive layer and a second layer over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species is implanted into the second layer. Source/drain regions are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: November 19, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brian A. Winstead, Konstantin V. Loiko, Voon-Yew Thean
  • Patent number: 8563394
    Abstract: Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: October 22, 2013
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES Inc.
    Inventors: Weipeng Li, Deleep R. Nair, Jae-Eun Park, Voon-Yew Thean, Young Way Teh
  • Publication number: 20120256268
    Abstract: Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.
    Type: Application
    Filed: April 11, 2011
    Publication date: October 11, 2012
    Applicants: GlobalFoundries, Inc., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Weipeng Li, Deleep R. Nair, Jae-Eun Park, Voon-Yew Thean, Young Way Teh
  • Patent number: 8106462
    Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: January 31, 2012
    Assignees: International Business Machines Corporation, Freescale Semiconductor, Inc., Infineon Technologies North America Corp., Chartered Semiconductor Manufacturing Ltd.
    Inventors: Xiangdong Chen, Weipeng Li, Anda C. Mocuta, Dae-Gyu Park, Melanie J. Sherony, Kenneth J. Stein, Haizhou Yin, Franck Arnaud, Jin-Ping Han, Laegu Kang, Yong Meng Lee, Young Way Teh, Voon-Yew Thean, Da Zhang
  • Patent number: 8039341
    Abstract: A semiconductor fabrication process includes masking a first region, e.g., an NMOS region, of a semiconductor wafer, e.g., a biaxial, tensile strained silicon on insulator (SOI) wafer and creating recesses in source/drain regions of a second wafer region, e.g., a PMOS region. The wafer is then annealed in an ambient that promotes migration of silicon. The source/drain recesses are filled with source/drain structures, e.g., by epitaxial growth. The anneal ambient may include a hydrogen bearing species, e.g., H2 or GeH2, maintained at a temperature in the range of approximately 800 to 1000° C. The second region may be silicon and the source/drain structures may be silicon germanium. Creating the recesses may include creating shallow recesses with a first etch process, performing an amorphizing implant to create an amorphous layer, performing an inert ambient anneal to recrystallize the amorphous layer, and deepening the shallow recesses with a second etch process.
    Type: Grant
    Filed: July 6, 2006
    Date of Patent: October 18, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Voon-Yew Thean, Bich-Yen Nguyen, Da Zhang
  • Publication number: 20110227136
    Abstract: The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.
    Type: Application
    Filed: March 22, 2010
    Publication date: September 22, 2011
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG ELECTRONICS CO., LTD., CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Jae-Eun Park, Weipeng Li, Deleep R. Nair, M. Dean Sciacca, Voon-Yew Thean, Ava Wan, Dong-Hun Lee, Yong-Meng Lee
  • Publication number: 20110220975
    Abstract: A semiconductor device is formed in a semiconductor layer. A gate stack is formed over the semiconductor layer and comprises a first conductive layer and a second layer over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species is implanted into the second layer. Source/drain regions are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack.
    Type: Application
    Filed: May 20, 2011
    Publication date: September 15, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Brian A. Winstead, Konstantin V. Loiko, Voon-Yew Thean
  • Patent number: 8003454
    Abstract: A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS device area (97) to form a relaxed semiconductor layer (91), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer (22) prior to forming the NMOS and PMOS gate structures (26, 36) overlying the channel regions, and then depositing a contact etch stop layer (53-56) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: August 23, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Da Zhang, Srikanth B. Samavedam, Voon-Yew Thean, Xiangdong Chen