Patents by Inventor Voya Rista Markovich
Voya Rista Markovich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6974915Abstract: The details of a printed wiring board (PWB) sub-assembly and the method of producing the same are described. The sub-assembly comprises a printed circuit board electrically joined through a plurality of connections to one or more area array devices, such as modules or printed wiring boards. The sub-assembly can serve as a part of an original assembly. The sub-assembly can function as an after market item that can be readily substituted as a replacement for a failed component wherein the dimensional space between the printed circuit board and one or both of the area array devices must provide sufficient clearance for surface mounted devices.Type: GrantFiled: November 1, 2004Date of Patent: December 13, 2005Assignee: International Business Machines CorporationInventors: William Louis Brodsky, Benson Chan, Michael Anthony Gaynes, Voya Rista Markovich
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Patent number: 6892451Abstract: The details of a printed wiring board (PWB) sub-assembly and the method of producing the same are described. The sub-assembly comprises a printed circuit board electrically joined through a plurality of connections to one or more area array devices, such as modules or printed wiring boards. The sub-assembly can serve as a part of an original assembly. The sub-assembly can function as an after market item that can be readily substituted as a replacement for a failed component wherein the dimensional space between the printed circuit board and one or both of the area array devices must provide sufficient clearance for surface mounted devices.Type: GrantFiled: February 10, 2003Date of Patent: May 17, 2005Assignee: International Business Machines CorporationInventors: William Louis Brodsky, Benson Chan, Michael Anthony Gaynes, Voya Rista Markovich
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Patent number: 6739048Abstract: A process of fabricating a circuitized structure is provided. The process includes the steps of providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in the dielectric film; sputtering a metal seed layer on the dielectric film and the microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.Type: GrantFiled: January 27, 2000Date of Patent: May 25, 2004Assignee: International Business Machines CorporationInventors: Gerald Walter Jones, Ross William Keesler, Voya Rista Markovich, William John Rudik, James Warren Wilson, William Earl Wilson
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Patent number: 6695623Abstract: A method and structure for electrically and mechanically interconnecting an array of printed circuit board contacts to an array of module contacts with a plurality of deformable resilient electrical conductors with two ends. Each of the conductor ends are electrically connected to one of the contact arrays. A portion of the conductor may deform longitudinally and laterally responsive to movement of the printed circuit board relative to the module responsive to heating and cooling cycles and mechanical vibrations, while maintaining the electrical connection of the contact arrays. An interposer with apertures extending through the interposer carries the conductors in the apertures and is used to align the conductors with the contacts. A method for excluding a rigid adhesive means from a portion of the resilient conductor is also taught.Type: GrantFiled: May 31, 2001Date of Patent: February 24, 2004Assignee: International Business Machines CorporationInventors: William Louis Brodsky, David V. Caletka, Michael Anthony Gaynes, Voya Rista Markovich
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Patent number: 6680440Abstract: The present invention provides new methods for electroless plating of metal particularly gold and copper onto substrates, such as circuitized substrates, which reduces processing steps, reduces metal consumption, and reduces the scraping of parts due to contamination. The method employs a permanent plating resist. The method for electrolessly plating metal onto a substrate, including the following steps: providing: an uncured, photoimagable, dielectric permanent plating resist comprising: from about 10 to 80% of phenoxy polyol resin which is the condensation product of epichlorohydrin and bisphenol A, having a molecular weight of from about 40,000 to 130,000; from about 20 to 90% of an epoxidized multifunctional bisphenol A formaldehyde novolac resin having a molecular weight of from about 4,000 to 10,000; from 0 to 50% of a diglycidyl ether of bisphenol A having a molecular weight of from about 600 to 2,500; and from about 0.Type: GrantFiled: February 23, 1998Date of Patent: January 20, 2004Assignee: International Business Machines CorporationInventors: David John Russell, Gerald Walter Jones, Heike Marcello, Voya Rista Markovich
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Publication number: 20030116351Abstract: The details of a printed wiring board (PWB) sub-assembly and the method of producing the same are described. The sub-assembly comprises a printed circuit board electrically joined through a plurality of connections to one or more area array devices, such as modules or printed wiring boards. The sub-assembly can serve as a part of an original assembly. The sub-assembly can function as an after market item that can be readily substituted as a replacement for a failed component wherein the dimensional space between the printed circuit board and one or both of the area array devices must provide sufficient clearance for surface mounted devices.Type: ApplicationFiled: February 10, 2003Publication date: June 26, 2003Applicant: International Business Machines CorporationInventors: William Louis Brodsky, Benson Chan, Michael Anthony Gaynes, Voya Rista Markovich
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Patent number: 6547974Abstract: A printed circuit board is produced by patterning a resist layer according to a circuit mask that defines desired circuit paths. The resist pattern layer is formed by removing the resist from the board in the desired circuit paths and a conductive material is plated onto the board in the resist voids defined by the circuit mask so that the height of the conductive material relative to the substrate equals or exceeds the height of the resist layer relative to the substrate. A low-reactive solution is applied over the conductive material and removes a surface portion of the conductive material. As the solution removes the conductive layer, it forms a film barrier and the solution composition changes, both of which substantially inhibits any further removal of the conductive material. Next, the film barrier is removed from the board allowing another film barrier to form stimulating the removal of further conductive material.Type: GrantFiled: June 27, 1995Date of Patent: April 15, 2003Assignee: International Business Machines CorporationInventors: Stanley Michael Albrechta, Christina Marie Boyko, Kathleen Lorraine Covert, Natalie Barbara Feilchenfeld, Voya Rista Markovich, William Earl Wilson, Michael Wozniak
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Patent number: 6545226Abstract: The details of a printed wiring board (PWB) sub-assembly and the method of producing the same are described. The sub-assembly comprises a printed circuit board electrically joined through a plurality of connections to one or more area array devices, such as modules or printed wiring boards. The sub-assembly can serve as a part of an original assembly. The sub-assembly can function as an after market item that can be readily substituted as a replacement for a failed component wherein the dimensional space between the printed circuit board and one or both of the area array devices must provide sufficient clearance for surface mounted devices.Type: GrantFiled: May 31, 2001Date of Patent: April 8, 2003Assignee: International Business Machines CorporationInventors: William Louis Brodsky, Benson Chan, Michael Anthony Gaynes, Voya Rista Markovich
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Publication number: 20020182900Abstract: A method and structure for electrically and mechanically interconnecting an array of printed circuit board contacts to an array of module contacts with a plurality of deformable resilient electrical conductors with two ends. Each of the conductor ends are electrically connected to one of the contact arrays. A portion of the conductor may deform longitudinally and laterally responsive to movement of the printed circuit board relative to the module responsive to heating and cooling cycles and mechanical vibrations, while maintaining the electrical connection of the contact arrays. An interposer with apertures extending through the interposer carries the conductors in the apertures and is used to align the conductors with the contacts. A method for excluding a rigid adhesive means from a portion of the resilient conductor is also taught.Type: ApplicationFiled: May 31, 2001Publication date: December 5, 2002Applicant: International Business Machines CorporationInventors: William Louis Brodsky, David V. Caletka, Michael Anthony Gaynes, Voya Rista Markovich
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Publication number: 20020179331Abstract: The details of a printed wiring board (PWB) sub-assembly and the method of producing the same are described. The sub-assembly comprises a printed circuit board electrically joined through a plurality of connections to one or more area array devices, such as modules or printed wiring boards. The sub-assembly can serve as a part of an original assembly. The sub-assembly can function as an after market item that can be readily substituted as a replacement for a failed component wherein the dimensional space between the printed circuit board and one or both of the area array devices must provide sufficient clearance for surface mounted devices.Type: ApplicationFiled: May 31, 2001Publication date: December 5, 2002Applicant: International Business Machines CorporationInventors: William Louis Brodsky, Benson Chan, Michael Anthony Gaynes, Voya Rista Markovich
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Patent number: 6436803Abstract: Circuit boards are manufactured by forming a substrate with a dielectric surface and laminating a metal foil onto the substrate. The metal foil is patterned to form a first wiring layer. A permanent photoimagable dielectric layer is formed over the wiring layer and via holes are formed through the dielectric layer over pads and conductors of the wiring layer. Holes are formed through the substrate and substrate surfaces including the photoimagable dielectric, walls of the via holes, and walls of the through holes subjected to an electroless copper plating process. The process includes seeding the surface, coating the surface with a first solution containing surfactant and electroplating in a second solution in which the level of surfactant is regulated by determining the surface tension and metering surfactant addition to the second solution depending on the determination of surface tension.Type: GrantFiled: April 23, 2001Date of Patent: August 20, 2002Assignee: International Business Machines CorporationInventors: Anilkumar Chinuprasad Bhatt, Roy Harvey Magnuson, Thomas Richard Miller, Voya Rista Markovich, Carlos J. Sambucetti, Stephen Leo Tisdale
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Patent number: 6414509Abstract: A method of testing semiconductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip carrier is provided. The chip carrier has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into conductive contact with the conductor pads on the chip carrier. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing, the chip may be removed from the substrate. Alternatively, the chip may be bonded through the dendritic conductor pads to the substrate after successful testing.Type: GrantFiled: May 3, 2000Date of Patent: July 2, 2002Assignee: International Business Machines CorporationInventors: Anilkumar Chinuprasad Bhatt, Leo Raymond Buda, Robert Douglas Edwards, Paul Joseph Hart, Anthony Paul Ingraham, Voya Rista Markovich, Jaynal Abedin Molla, Richard Gerald Murphy, George John Saxenmeyer, Jr., George Frederick Walker, Bette Jaye Whalen, Richard Stuart Zarr
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Publication number: 20020078562Abstract: A process of fabricating a circuitized substrate is provided which comprising the steps of: providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in said dielectric film; sputtering a metal seed layer on the dielectric film and in said microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.Type: ApplicationFiled: January 27, 2000Publication date: June 27, 2002Inventors: Gerald Walter Jones, Ross William Keesler, Voya Rista Markovich, William John Rudik, James Warren Wilson, William Earl Wilson
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Publication number: 20010033889Abstract: The present invention provides a method for electrolessly depositing metal onto a substrate, comprising: exposing a surface of the substrate to a first solution including a surfactant; and exposing the surface, having residual surfactant from the first solution thereon, to a second solution including ions of an electroconductive metal element for plating the surface with the electroconductive metal while exposed to the second solution; wherein the surface is exposed to the first solution immediately prior to exposing the surface to the second solution.Type: ApplicationFiled: April 23, 2001Publication date: October 25, 2001Inventors: Anilkumar Chinuprasad Bhatt, Roy Harvey Magnuson, Thomas Richard Miller, Voya Rista Markovich, Carlos J. Sambucetti, Stephen Leo Tisdale
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Patent number: 6268016Abstract: Circuit boards are manufactured by forming a substrate with a dielectric surface and laminating a metal foil onto the substrate. The metal foil is patterned to form a first wiring layer. A permanent photoimagable dielectric layer is formed over the wiring layer and via holes are formed through the dielectric layer over pads and conductors of the wiring layer. Holes are formed through the substrate and substrate surfaces including the photoimagable dielectric, walls of the via holes, and walls of the through holes subjected to an electroless copper plating process. The process includes seeding the surface, coating the surface with a first solution containing surfactant and electroplating in a second solution in which the level of surfactant is regulated by determining the surface tension and metering surfactant addition to the second solution depending on the determination of surface tension.Type: GrantFiled: June 28, 1996Date of Patent: July 31, 2001Assignee: International Business Machines CorporationInventors: Anilkumar Chinuprasad Bhatt, Roy Harvey Magnuson, Thomas Richard Miller, Voya Rista Markovich, Carlos J. Sambucetti, Stephen Leo Tisdale
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Patent number: 6194024Abstract: The present invention permits solder joints to be made directly to via and through holes without the solder being wicked into the vias or through holes, by filling plated through holes with an epoxy or cyanate fill composition. When cured and overplated, the fill composition provides support for the solder joint and provides a flat solderable surface for the inter-connection. In certain embodiments, the cured fill compositions, offer a further advantage of being conductive. The invention also relates to several novel methods for filling through holes with such fill compositions, and to resistors located in through holes and vias.Type: GrantFiled: June 6, 1995Date of Patent: February 27, 2001Assignee: International Business Machines CorporationInventors: Roy Lynn Arldt, Christina Marie Boyko, Burtran Joe Cayson, Richard Michael Kozlowski, Joseph Duane Kulesza, John Matthew Lauffer, Philip Chihchau Liu, Voya Rista Markovich, Issa Said Mahmoud, James Francis Muska, Kostas Papathomas, Joseph Gene Sabia, Richard Anthony Schumacher
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Patent number: 6178093Abstract: An information handling system is provided which comprises: a metal enclosure; at least one circuit assembly positioned within said metal enclosure, said circuit assembly including a circuitized substrate having at least one dielectric interior layer including a first surface and at least one hole therein; means for providing electrical power to said circuitized substrate within said metal enclosure; a filler material, wherein said filler material substantially fills said at least one hole within said at least one dielectric interior layer; a first wiring layer positioned on said first surface of said at least one dielectric interior layer, wherein said first wiring layer substantially covers said at least one hole having said filler material therein, said first wiring layer assisting in retaining said filler material within said at least one hole in said at least one dielectric interior layer; a first dielectric photoresist layer positioned on said first wiring layer and on said first surface of said at leaType: GrantFiled: March 3, 1998Date of Patent: January 23, 2001Assignee: International Business Machines CorporationInventors: Anilkumar Chinuprasad Bhatt, Donald Herman Glatzel, Allen F. Moring, Voya Rista Markovich, Kostas Papathomas, David John Russell
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Patent number: 6150255Abstract: According to the present invention a technique for providing a planarized substrate with dendritic connections of solder balls, especially a multi-layer ceramic substrate is provided. In the case where the substrate has a raised central portion on the top surface on which are disposed top surface metallurgy pads, a layer of conformable photoimagable material is placed over the top surface.The photoimagable material is exposed and developed in a pattern corresponding to the pattern of the top surface metallurgy pads to form vias in the photoimagable material. Copper is plated in the vias in contact with the top surface metallurgy pads. The exposed surface of the photoimagable surface is then planarized, preferably by mechanical polishing to form a flat planar surface, with the ends of the vias exposed. Dendritic connector pads are then grown on the exposed ends of the vias to which solder ball connections of an I/C chip are releasably connected.Type: GrantFiled: August 13, 1999Date of Patent: November 21, 2000Assignee: International Business Machines CorporationInventors: Francis Joseph Downes, Jr., Stephen Joseph Fuerniss, Gary Ray Hill, Anthony Paul Ingraham, Voya Rista Markovich, Jaynal Abedin Molla
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Patent number: 6138350Abstract: A process for manufacturing circuit boards comprising providing a circuitized substrate having a dielectric surface, providing a peel apart structure including a metal layer and a peelable film, laminating the peel apart structure to the circuitized substrate with the metal layer positioned adjacent said dielectric surface, forming holes in the circuitized substrate through the peel apart structure, applying a filler material including an organic base to the peel apart structure, applying a sacrificial film onto the filler material, and applying sufficient heat and pressure to the sacrificial film to force the filler material into the holes to substantially fill the holes is provided.Type: GrantFiled: February 25, 1998Date of Patent: October 31, 2000Assignee: International Business Machines CorporationInventors: Anilkumar Chinuprasad Bhatt, Donald Herman Glatzel, Allen F. Moring, Voya Rista Markovich, Kostas Papathomas, David John Russell
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Patent number: 6134772Abstract: The present invention permits solder joints to be made directly to via and through holes without the solder being wicked into the vias or through holes, by filling plated through holes with an epoxy or cyanate fill composition. When cured and overplated, the fill composition provides support for the solder joint and provides a flat solderable surface for the inter-connection. In certain embodiments, the cured fill compositions, offer a further advantage of being conductive. The invention also relates to several novel methods for filling through holes with such fill compositions, and to resistors located in through holes and vias.Type: GrantFiled: December 18, 1998Date of Patent: October 24, 2000Assignee: International Business Machines CorporationInventors: Roy Lynn Arldt, Christina Marie Boyko, Burtran Joe Cayson, Richard Michael Kozlowski, Joseph Duane Kulesza, John Matthew Lauffer, Philip Chihchau Liu, Voya Rista Markovich, Issa Said Mahmoud, James Francis Muska, Kostas Papathomas, Joseph Gene Sabia, Richard Anthony Schumacher