Patents by Inventor Voya Rista Markovich
Voya Rista Markovich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5800858Abstract: A halogenated polymeric material is exposed to a reducing agent and/or an electrolyte and applied voltage to render exposed portions capable of being metallized and of being etched. The exposed portions can also be doped to thereby induce electrical conductivity therein. Also, new structures containing a free standing halogenated polymeric-containing layer and electrical conductive pattern thereon are provided.Type: GrantFiled: September 12, 1996Date of Patent: September 1, 1998Assignee: International Business Machines CorporationInventors: Harry Randall Bickford, Peter J. Duke, Elizabeth Foster, Martin Goldberg, Voya Rista Markovich, Linda Matthew, Donald G. McBride, Terrence Robert O'Toole, Stephen Leo Tisdale, Alfred Viehbeck
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Patent number: 5766670Abstract: The present invention permits solder joints to be made directly to via and through holes without the solder being wicked into the vias or through holes, by filling plated through holes with an epoxy or cyanate fill composition. When cured and overplated, the fill composition provides support for the solder joint and provides a flat solderable surface for the inter-connection. In certain embodiments, the cured fill compositions, offer a further advantage of being conductive. The invention also relates to several novel methods for filling through holes with such fill compositions, and to resistors located in through holes and vias.Type: GrantFiled: November 17, 1993Date of Patent: June 16, 1998Inventors: Roy Lynn Arldt, Christina Marie Boyko, Burtran Joe Cayson, Richard Michael Kozlowski, Joseph Duane Kulesza, John Matthew Lauffer, Philip Chihchau Liu, Voya Rista Markovich, Issa Said Mahmoud, James Francis Muska, Kostas Papathomas, Joseph Gene Sabia, Richard Anthony Schumacher
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Patent number: 5759427Abstract: A technique for chemically planarizing an exposed surface of metal on a substrate to a pre-determined thickness is provided. The substrate has an exposed metal surface such as copper circuitry on a dielectric substrate which is to be planarized. Typically, this will be circuitization extending above a photoresist layer. A planarizing head is rotated against the substrate, with the planarizing head in contact with the metal surface on the substrate. A chemical etchant, essentially free of abrasive material, is continuously supplied to the interface between the metal surface and the planarizing head. The planarizing continues until a predetermined thickness of the metal has been reached. In circuit board manufacturing, this will form a surface co-planar with the photoresist. In some instances where significant height reduction is required, thus requiring significant metal removal, several passes of the substrate may be required or a device with multiple heads may be used.Type: GrantFiled: August 28, 1996Date of Patent: June 2, 1998Assignee: International Business Machines CorporationInventors: Edward Cibulsky, Gerald Andrew Kiballa, Voya Rista Markovich, Gary Leigh Newman, John Francis Prikazsky, Michael Wozniak
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Patent number: 5730890Abstract: A halogenated polymeric material is exposed to a reducing agent and/or an electrolyte and applied voltage to render exposed portions capable of being metallized and of being etched. The exposed portions can also be doped to thereby induce electrical conductivity therein. Also, new structures containing a free standing halogenated polymeric-containing layer and electrical conductive pattern thereon are provided.Type: GrantFiled: September 12, 1996Date of Patent: March 24, 1998Assignee: Internationl Business Machines CorporationInventors: Harry Randall Bickford, Elizabeth Foster, Martin Goldberg, Voya Rista Markovich, Linda Matthew, Stephen Leo Tisdale, Alfred Viehbeck
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Patent number: 5709906Abstract: A method of treating a halogenated polymeric-containing substrate including exposing at least portions of the halogenated polymeric-containing substrate to a composition containing a reducing agent and an aprotic solvent selected from the group consisting of nitriles, nitro compounds, amides, esters, carbonates, oxides, sulfo compounds and mixtures thereof. The solvent is free of ethers, amines, ammonia. The composition is prepared by reacting a metal with an organic compound selected from the group consisting of polyaryl compounds, aromatic carbonyl containing compounds, aromatic nitriles, and aromatic heterocyclic nitrogen containing compounds in a reaction solvent that does not react with the metal but permits reaction between the metal and the organic compound to thereby provide the reducing agent. The reducing agent is isolated from the reaction solvent to obtain a reaction product as a solid. The reaction product is added to the aprotic solvent.Type: GrantFiled: June 16, 1995Date of Patent: January 20, 1998Assignee: International Business Machines CorporationInventors: Harry Randall Bickford, Peter J. Duke, Elizabeth Foster, Martin Goldberg, Voya Rista Markovich, Linda Matthew, Donald G. McBride, Terrence Robert O'Toole, Stephen Leo Tisdale, Alfred Viehbeck
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Patent number: 5707893Abstract: A process for making a circuitized substrate is defined wherein the substrate is treated with two different, e.g., additive and subtractive, metallization processes. The process is thus able to effectively produce substrates including conductive features, e.g., high density circuit lines and chip heat-sinking pads, of two different degrees of resolution in a cost effective and expeditious manner. The resulting product is also defined.Type: GrantFiled: December 1, 1995Date of Patent: January 13, 1998Assignee: International Business Machines CorporationInventors: Anilkumar Chinuprasad Bhatt, Ashwinkumar Chinuprasad Bhatt, Robert Jeffrey Day, Thomas Patrick Duffy, Jeffrey Alan Knight, Richard William Malek, Voya Rista Markovich
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Patent number: 5685070Abstract: A printed circuit board or card for direct chip attachment that includes at least one power core, at least one signal plane that is adjacent to the power core, and plated through holes for electrical connection is provided. In addition, a layer of dielectric material is adjacent the power core and a circuitized conductive layer is adjacent the dielectric material, followed by a layer of photosensitive dielectric material adjacent the conductive layer. Photodeveloped blind vias for subsequent connection to the power core and drilled blind vias for subsequent connection to the signal plane are provided. Also provided is process for fabricating the printed circuit board or card for direct chip attachment.Type: GrantFiled: January 19, 1995Date of Patent: November 11, 1997Assignee: International Business Machines CorporationInventors: Warren Alan Alpaugh, Voya Rista Markovich, Ajit Kumar Trivedi, Richard Stuart Zarr
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Patent number: 5672260Abstract: Small, closely spaced deposits of solder materials may be formed with high volumetric accuracy and uniformity of shape by depositing a layer of conductive material over surfaces of a dielectric layer having apertures or recesses (e.g. blind apertures) and conductors and/or pads exposed by those apertures or recesses, masking regions of the conductive material with a further patterned dielectric layer, electroplating solder materials onto regions of the conductive material exposed by the mask, removing the mask and portions of the conductive material by selective etching and reflowing solder away from at least a portion of the surfaces of the apertured dielectric layer. Uniformity of electroplating within blind apertures is enhanced by a combination of fluid jet sparging and cathode agitation. Excess conductor material in the resulting solder deposit can be avoided by replacing conductor material with a constituent component of a solder material in an immersion bath prior to electroplating.Type: GrantFiled: April 17, 1996Date of Patent: September 30, 1997Assignee: International Business Machines CorporationInventors: Charles Francis Carey, Kenneth Michael Fallon, Voya Rista Markovich, Douglas Oliver Powell, Gary Paul Vlasak, Richard Stuart Zarr
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Patent number: 5672980Abstract: A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.Type: GrantFiled: February 15, 1996Date of Patent: September 30, 1997Assignee: International Business Machines CorporationInventors: Richard Gordon Charlton, George Charles Correia, Mark Andrew Couture, Gary Ray Hill, Kibby Barth Horsford, Anthony Paul Ingraham, Michael David Lowell, Voya Rista Markovich, Gordon Charles Osborne, Jr., Mark Vincent Pierson
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Patent number: 5667934Abstract: A thermally stable photoimaging composition and a method of using the same, especially on circuit boards as a solder mask is provided. The composition includes a polymerizable resin or resin system, a cationic photoinitiator, a solvent, and an optically transparent ceramic filler. Preferably, the composition has a coefficient of thermal expansion of about 28-40 ppm/.degree.C., which closely matches the coefficient of thermal expansion of the solder used on the circuit board components.Type: GrantFiled: October 9, 1990Date of Patent: September 16, 1997Assignee: International Business Machines CorporationInventors: Voya Rista Markovich, Ashit Arvind Mehta, Eugene Roman Skarvinko, David Wei Wang
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Patent number: 5665526Abstract: A thermally stable photoimaging composition and a method of using the same, especially on circuit boards as a solder mask is provided. The composition includes a polymerizable resin or resin system, a cationic photoinitiator, a solvent, and an optically transparent ceramic filler. Preferably, the composition has a coefficient of thermal expansion of about 28-40 ppm/.degree. C., which closely matches the coefficient of thermal expansion of the solder used on the circuit board components.Type: GrantFiled: June 6, 1995Date of Patent: September 9, 1997Assignee: International Business Machines CorporationInventors: Voya Rista Markovich, Ashit Arvind Mehta, Eugene Roman Skarvinko, David Wei Wang
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Patent number: 5659256Abstract: A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.Type: GrantFiled: February 15, 1996Date of Patent: August 19, 1997Assignee: International Business Machines CorporationInventors: Richard Gordon Charlton, George Charles Correia, Mark Andrew Couture, Gary Ray Hill, Kibby Barth Horsford, Anthony Paul Ingraham, Michael David Lowell, Voya Rista Markovich, Gordon Charles Osborne, Jr., Mark Vincent Pierson
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Patent number: 5656139Abstract: Small, closely spaced deposits of solder materials may be formed with high volumetric accuracy and uniformity of shape by depositing a layer of conductive material over surfaces of a dielectric layer having apertures or recesses (e.g. blind apertures) and conductors and/or pads exposed by those apertures or recesses, masking regions of the conductive material with a further patterned dielectric layer, electroplating solder materials onto regions of the conductive material exposed by the mask, removing the mask and portions of the conductive material by selective etching and reflowing solder away from at least a portion of the surfaces of the apertured dielectric layer. Uniformity of electroplating within blind apertures is enhanced by a combination of fluid jet sparging and cathode agitation. Excess conductor material in the resulting solder deposit can be avoided by replacing conductor material with a constituent component of a solder material in an immersion bath prior to electroplating.Type: GrantFiled: January 16, 1996Date of Patent: August 12, 1997Assignee: International Business Machines CorporationInventors: Charles Francis Carey, Kenneth Michael Fallon, Voya Rista Markovich, Douglas Oliver Powell, Gary Paul Vlasak, Richard Stuart Zarr
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Patent number: 5229550Abstract: A structure and method are disclosed for making high density circuit board. Using photosensitive or other dielectric materials over a circuitized power core, vias and lands are opened up, filled with joining metal and aligned with the next level, eliminating a major registration problem in building up a high density composite and reducing the number of steps in the manufacturing process.Type: GrantFiled: March 31, 1992Date of Patent: July 20, 1993Assignee: International Business Machines CorporationInventors: Perminder S. Bindra, Dennis A. Canfield, Voya Rista Markovich, Jeffrey McKeveny, Robert E. Ruane, Edwin L. Thomas