Patents by Inventor Voya Rista Markovich
Voya Rista Markovich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6131279Abstract: A process of fabricating a circuitized substrate is provided which comprising the steps of: providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in said dielectric film; sputtering a metal seed layer on the dielectric film and in said microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.Type: GrantFiled: January 8, 1998Date of Patent: October 17, 2000Assignee: International Business Machines CorporationInventors: Gerald Walter Jones, Ross William Keesler, Voya Rista Markovich, William John Rudik, James Warren Wilson, William Earl Wilson
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Patent number: 6127025Abstract: Circuit boards are manufactured by forming a substrate with a dielectric surface, laminating a metal foil and a peelable film to the substrate, and forming holes in the substrate through the peelable film and foil. A filler material with an organic base may be filled with electroconductive particles or dielectric thermoconductive particles. The filler material is deposited onto a sacrificial carrier and the filler material is heated to at least partially cure it. The filler material is laminated onto the peelable film with sufficient heat and pressure to force the filler material to fill the holes. For thermoconductive filler the holes are filled sufficient for electrical connection through the holes. The peelable layer, sacrificial carrier and filler material remaining therebetween are peeled off the copper foil. The filler material is abraded to the level of the foil and is then copper plated. The copper is patterned to form a wiring layer.Type: GrantFiled: March 10, 1998Date of Patent: October 3, 2000Assignee: International Business Machines CorporationInventors: Anilkumar Chinuprasad Bhatt, Donald Herman Glatzel, Allen F. Moring, Voya Rista Markovich, Kostas Papathomas, David John Russell
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Patent number: 6114019Abstract: A circuit assembly that includes a circuitized substrate having a dielectric interior layer with a first surface and at least one hole therein. A filler material substantially fills the hole within the dielectric interior layer. A first wiring layer is positioned on the first surface of the dielectric interior layer, wherein the first wiring layer substantially covers the hole and assists in retaining the filler material within the hole in the dielectric interior layer. A first dielectric photoresist layer is positioned on the first wiring layer and on the first surface of the dielectric interior layer. The first dielectric photoresist layer also includes at least one hole therein. The filler material also substantially fills the hole within the first dielectric photoresist layer. A second wiring layer is positioned on the first dielectric photoresist layer and includes a plurality of conductive pads as part thereof.Type: GrantFiled: March 2, 1998Date of Patent: September 5, 2000Assignee: International Business Machines CorporationInventors: Anilkumar Chinuprasad Bhatt, Donald Herman Glatzel, Allen F. Moring, Voya Rista Markovich, Kostas Papathomas, David John Russell
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Patent number: 6106891Abstract: The present invention permits solder joints to be made directly to via and through holes without the solder being wicked into the vias or through holes, by filling plated through holes with an epoxy or cyanate fill composition. When cured and overplated, the fill composition provides support for the solder joint and provides a flat solderable surface for the inter-connection. In certain embodiments, the cured fill compositions, offer a further advantage of being conductive. The invention also relates to several novel methods for filling through holes with such fill compositions, and to resistors located in through holes and vias.Type: GrantFiled: December 18, 1998Date of Patent: August 22, 2000Assignee: International Business Machines CorporationInventors: Joseph Duane Kulesza, Voya Rista Markovich, Kostas Papathomas, Joseph Gene Sabia
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Patent number: 6093335Abstract: A method for planarizing an exposed metal surface on a substrate is provided in which surface irregularities are eliminated. A photoresist layer is first removed from the substrate. Then a conformal planarizing head is placed in contact with the metal surface while chemical etchant essentially free of abrasives is supplied to an interface between the metal substrate and the planarizing head. The surface is then planarized until it is free of irregularties.Type: GrantFiled: November 20, 1997Date of Patent: July 25, 2000Assignee: International Business Machines CorporationInventors: Ashwinkumar C. Bhatt, John Christopher Camp, Subahu Dhirubhai Desai, Voya Rista Markovich, Michael Wozniak
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Patent number: 6027858Abstract: A process of tenting plated through holes with a photoimageable dielectric is provided which includes a dielectric film comprising a photoimageable epoxy based resin layer and a peelable polyester layer. In accordance with the process of the present invention, the peelable polyester layer of the dielectric film is removed prior to baking, developing, patterning or curing the structure.Type: GrantFiled: June 6, 1997Date of Patent: February 22, 2000Assignee: International Business Machines CorporationInventors: Gerald Walter Jones, Ross William Keesler, Voya Rista Markovich, Heinke Marcello, James Warren Wilson, William Earl Wilson
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Patent number: 6000129Abstract: Circuit boards are manufactured by forming a substrate with a dielectric surface, laminating a metal foil to the substrate, and forming holes in the substrate through the foil. A filler material with an organic base may be filled with electroconductive particles or dielectric thermoconductive particles. The filler material is deposited into the holes and is heated to at least partially cure it. The surface of the filler material is seeded and electrolessly plated to form a conductive coating on the metal foil and the filler material. The coating is then patterned to form a wiring layer. A second set of holes may be formed in the circuitized substrate after the hole filling step, which are also electrolessly plated.Type: GrantFiled: March 12, 1998Date of Patent: December 14, 1999Assignee: International Business Machines CorporationInventors: Anilkumar Chinuprasad Bhatt, Donald Herman Glatzel, Allen F. Moring, Voya Rista Markovich, Kostas Papathomas, David John Russell
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Patent number: 5997997Abstract: The present invention provides a novel method of reducing the amount of seed deposited on polymeric dielectric surfaces. The method comprises the following steps: providing a work-piece coated with a polymeric dielectric layer; baking the work-piece to modify the surface of the polymeric dielectric layer; then applying the seed to polymeric dielectric layer and electrolessly plating metal to the seed layer. The invention also relates to a circuit board produced by the method of the present invention.Type: GrantFiled: June 13, 1997Date of Patent: December 7, 1999Assignee: International Business Machines Corp.Inventors: Anastasios Peter Angelopoulos, Gerald Walter Jones, Luis Jesus Matienzo, Thomas Richard Miller, Voya Rista Markovich
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Patent number: 5981880Abstract: A printed circuit board for use in an electronic device package such as a ball grid array package or organic chip carrier package includes a glass-free dielectric for separating and insulating power cores, circuitry or plated through holes from each other to prevent shorts caused by a migration of conductive material along glass-based prepreg substrates.Type: GrantFiled: August 20, 1996Date of Patent: November 9, 1999Assignee: International Business Machines CorporationInventors: Bernd Karl-Heinz Appelt, Anilkumar Chinuprasad Bhatt, James W. Fuller, Jr., John Matthew Lauffer, Voya Rista Markovich, William John Rudik, William Earl Wilson
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Patent number: 5940729Abstract: According to the present invention a technique for providing a planarized substrate with dendritic connections of solder balls, especially a multi-layer ceramic substrate is provided. In the case where the substrate has a raised central portion on the top surface on which are disposed top surface metallurgy pads, a layer of conformable photoimagable material is placed over the top surface.The photoimagable material is exposed and developed in a pattern corresponding to the pattern of the top surface metallurgy pads to form vias in the photoimagable material. Copper is plated in the vias in contact with the top surface metallurgy pads. The exposed surface of the photoimagable surface is then planarized, preferably by mechanical polishing to form a flat planar surface, with the ends of the vias exposed. Dendritic connector pads are then grown on the exposed ends of the vias to which solder ball connections of an I/C chip are releasably connected.Type: GrantFiled: April 17, 1996Date of Patent: August 17, 1999Assignee: International Business Machines Corp.Inventors: Francis Joseph Downes, Jr., Stephen Joseph Fuerniss, Gary Ray Hill, Anthony Paul Ingraham, Voya Rista Markovich, Jaynal Abedin Molla
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Patent number: 5935652Abstract: The present invention provides a novel method of reducing the amount of seed deposited on polymeric dielectric surfaces. The method comprises the following steps: providing a work-piece coated with a polymeric dielectric layer; baking the work-piece to modify the surface of the polymeric dielectric layer; then applying the seed to polymeric dielectric layer and electrolessly plating metal to the seed layer. The invention also relates to a circuit board produced by the method of the present invention.Type: GrantFiled: March 23, 1998Date of Patent: August 10, 1999Assignee: International Business Machines Corp.Inventors: Anastasios Peter Angelopoulos, Gerald Walter Jones, Luis Jesus Matienzo, Thomas Richard Miller, Voya Rista Markovich
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Patent number: 5922517Abstract: Bridging between electrically conductive circuit features during conformal plating is prevented by avoiding the deposition of catalytic seed material onto non-circuit areas of the substrate. Preparatory to forming electrical circuit features on a nonconductive substrate by the full additive process, extraneous seed material is either trapped between two layers of a photoimageable film, whereby it is unavailable during plating, or deposited on the surface of an aqueous photoimageable film, which is removed prior to plating. The method embodying the present invention eliminates the need for seed removal after initial plating and prior to conformal plating of a precious metal over the initial plating.Type: GrantFiled: June 12, 1996Date of Patent: July 13, 1999Assignee: International Business Machines CorporationInventors: Anilkumar Chinuprasad Bhatt, Ashwinkumar C. Bhatt, Voya Rista Markovich, William Earl Wilson, Gerald Walter Jones
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Patent number: 5919596Abstract: Disclosed is an admixture which is curable to form a crack resistant, photosensitive polycyanurate resist. Also disclosed is a structure for its use and process of making. The resist can be tailored to be either positively or negatively sensitive to actinic radiation. Because of its improved thermal and mechanical properties, the cured resist is suitable for use at high temperature, such as in electronic packaging applications.Type: GrantFiled: February 11, 1997Date of Patent: July 6, 1999Assignee: International Business Machines CorporationInventors: Jeffrey C. Hedrick, Konstantinos Papathomas, Stephen L. Tisdale, Alfred Viehbeck, Jeffrey D. Gelorme, Voya Rista Markovich, Thomas H. Lewis, Stephen Joseph Fuerniss
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Patent number: 5905018Abstract: Bridging between electrically conductive circuit features during conformal plating is prevented by avoiding the deposition of catalytic seed material onto non-circuit areas of the substrate. Preparatory to forming electrical circuit features on a nonconductive substrate by the full additive process, extraneous seed material is either trapped between two layers of a photoimageable film, whereby it is unavailable during plating, or deposited on the surface of an aqueous photoimageable film, which is removed prior to plating. The method embodying the present invention eliminates the need for seed removal after initial plating and prior to conformal plating of a precious metal over the initial plating.Type: GrantFiled: October 24, 1997Date of Patent: May 18, 1999Assignee: International Business Machines CorporationInventors: Anilkumar Chinuprasad Bhatt, Ashwinkumar C. Bhatt, Voya Rista Markovich, William Earl Wilson, Gerald Walter Jones
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Patent number: 5893983Abstract: A technique for polishing an exposed surface of metal on a substrate to remove defects from mechanical working of metals, such as burrs and pigtails resulting from drilling, and defects from plating, such as nodules and depressions, is provided. The substrate has an exposed metal surface such as copper thereon which is to be treated to remove defects. A planarizing or polishing head, preferably a rotating roller, is provided which is continuously rotating with respect to the substrate, with the head in contact with the metal surface on the substrate. A chemical etchant, essentially free of abrasive material, is continuously supplied to the interface between the metal surface and the head. The treating and polishing continues until the defects have been removed or reduced to an acceptable value. In some instances where significant height reduction is required, thus requiring significant metal removal, several passes of the substrate may be required or a device with multiple heads may be used.Type: GrantFiled: November 19, 1996Date of Patent: April 13, 1999Assignee: International Business Machines CorporationInventors: John Joseph Konrad, Voya Rista Markovich, George Frederick Reel, Jose Antonio Rios, Timothy Leroy Wells, Michael Wozniak
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Patent number: 5887345Abstract: The present invention permits solder joints to be made directly to via and through holes without the solder being wicked into the vias or through holes, by filling plated through holes with an epoxy or cyanate fill composition. When cured and overplated, the fill composition provides support for the solder joint and provides a flat solderable surface for the inter-connection. In certain embodiments, the cured fill compositions, offer a further advantage of being conductive. The invention also relates to several novel methods for filling through holes with such fill compositions, and to resistors located in through holes and vias.Type: GrantFiled: October 30, 1997Date of Patent: March 30, 1999Assignee: International Business Machines CorporationInventors: Joseph Duane Kulesza, Voya Rista Markovich, Kostas Papathomas, Joseph Gene Sabia
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Patent number: 5876842Abstract: A modular structure for providing electrical interconnections achieves greatly increased wiring density by forming vias and wiring patterns by chemical (e.g. lithographic) processes rather than by mechanical processes such as punching of vias and screening patterns of conductive paste. A basic module is a power core comprising an apertured metallic foil with an insulator applied to surfaces thereof, extending through at least one aperture and exposing the metallic foil in at least one aperture. The foil in the power core provides stiffness to facilitate subsequent handling and electrical shielding between conductive layers as well as a potential power connection. Via connections of increased conductivity and robustness are formed by plating the interior of vias after lamination of a desired combination of power cores and signal cores.Type: GrantFiled: December 27, 1996Date of Patent: March 2, 1999Assignee: International Business Machines CorporationInventors: Thomas Patrick Duffy, Harold Kohn, Voya Rista Markovich, David John Russell
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Patent number: 5874154Abstract: A structure including a halogenated polymeric-containing layer. At least a portion of a surface of the halogenated polymeric-containing layer is electrochemically reduced. An electrically conductive pattern is provided over at least a portion of the electrochemically reduced portion of the halogenated polymeric-containing layer.Type: GrantFiled: September 12, 1996Date of Patent: February 23, 1999Assignee: International Business Machines CorporationInventors: Harry Randall Bickford, Peter J. Duke, Elizabeth Foster, Martin Goldberg, Voya Rista Markovich, Linda Matthew, Donald G. McBride, Terrence Robert O'Toole, Stephen Leo Tisdale, Alfred Viehbeck
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Patent number: 5822856Abstract: Circuit boards are manufactured by forming a substrate with a dielectric surface, laminating a metal foil and a peelable film to the substrate, and forming holes in the substrate through the peelable film and foil. A filler material with an organic base may be filled with electroconductive particles or dielectric thermoconductive particles. The filler material is laminated onto the peelable film with sufficient heat and pressure to force the filler material to fill the holes. For thermoconductive filler the holes are filled sufficient for electrical connection through the holes. The filler material is abraded to the level of the foil and is then copper plated. The copper is patterned to form a wiring layer. A permanent dielectric photoresist layer is formed over the wiring layer and via holes are formed through the photoimageable dielectric over pads and conductors of the wiring layer.Type: GrantFiled: June 28, 1996Date of Patent: October 20, 1998Assignee: International Business Machines CorporationInventors: Anilkumar Chinuprasad Bhatt, Donald Herman Glatzel, Allen F. Moring, Voya Rista Markovich, Kostas Papathomas, David John Russell
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Patent number: 5817405Abstract: A process for making a circuitized substrate is defined wherein the substrate is treated with two different, e.g., additive and subtractive, metallization processes. The process is thus able to effectively produce substrates including conductive features, e. g., high density circuit lines and chip heat-sinking pads, of two different degrees of resolution in a cost effective and expeditious manner. The resulting product is also defined.Type: GrantFiled: February 4, 1997Date of Patent: October 6, 1998Assignee: International Business Machines CorporationInventors: Anikumar Chinuprasad Bhatt, Ashwinkumar Chinuprasad Bhatt, Robert Jeffrey Day, Thomas Patrick Duffy, Jeffrey Alan Knight, Richard William Malek, Voya Rista Markovich