Abstract: A surface mount semiconductor device has a semiconductor die encapsulated in a molding compound. Electrical contact elements of an intermediate set are disposed on the molding compound. A set of coated wires electrically connect bonding pads of the semiconductor die and the electrical contact elements of the intermediate set. A layer of insulating material covers the coated wires, the die and the electrical contact elements of the intermediate set. Electrically conductive elements are exposed at an external surface of the layer of insulating material and contact respective electrical contact elements of the intermediate set through the layer of insulating material.

Abstract: A wire capable of conducting electrical current has a polymer core and a coating layer surrounding the core. The coating layer, which may be, for example, gold or copper, conducts electrical current and the core provides strength so that the wire is able to withstand bending and breakage. Among other things, the polymer core wire is useful for connecting an integrated circuit to a lead frame or substrate.

Abstract: A method of packaging semiconductor integrated circuits, including the steps of providing a transfer film and forming a patterned, conductive layer on a surface of the transfer film. A first semiconductor integrated circuit (IC) then is attached to the transfer film, where an active side of the first IC is attached to the transfer film. A second semiconductor IC then is attached to the first IC, where a bottom side of the second IC is attached to a bottom side of the first IC. Die pads on an active surface of the second IC are electrically connected to the conductive layer with wires and then a resin material is provided on one side of the transfer film to encapsulate the first and second ICs, the wires and a portion of the conductive layer. Next the transfer film is removed, which exposes the active side of the first IC and the conductive layer.

Abstract: A semiconductor package (10) including a pressure sensor die (14) has an interconnect layer (22) formed over a first major surface of the pressure sensor die (14). An encapsulant (18) encapsulates a second major surface and sides of the pressure sensor die (14). A cavity (32) extends through the interconnect layer (22) to the first major surface of the pressure sensor die (14). The interconnect layer (22) allows for the assembly of a low-profile package.

Abstract: A semiconductor package (10) including a pressure sensor die (14) has an interconnect layer (22) formed over a first major surface of the pressure sensor die (14). An encapsulant (18) encapsulates a second major surface and sides of the pressure sensor die (14). A cavity (32) extends through the interconnect layer (22) to the first major surface of the pressure sensor die (14). The interconnect layer (22) allows for the assembly of a low-profile package.

Abstract: A method of forming a semiconductor package (10) including forming a plurality of cavities (14) in a substrate (12). An electrically conductive pattern (16) is formed on the substrate (12) and over the cavities (14). An electrically insulating layer (22) is formed over the substrate (12) and the electrically conductive pattern (16). A plurality of vias (24) is formed in the electrically insulating layer (22). An integrated circuit (IC) die (28) is attached to the electrically insulating layer (22) and electrically connected to the vias (24) such that the IC die (28) is connected to the electrically conductive pattern (16). A molding operation is performed to encapsulate the IC die (28). The substrate (12) is removed such that the electrically conductive pattern (16) is exposed.

Abstract: A method of manufacturing a semiconductor wafer for dicing includes providing a semiconductor wafer including a substrate and a plurality of upper layers on the substrate that form a formation of die areas. The formation is arranged so that adjacent die areas are separated by a path for a dicing tool. Within each path, a pair of spaced apart lines is fabricated. Each line defines a dicing edge of a respective path and has at least one trench extending between a top surface of the wafer and the substrate. Each trench is filled with a stress absorbing material for reducing die tool induced stress on the die areas during dicing.

Abstract: A method of forming a semiconductor package (10) including forming a plurality of cavities (14) in a substrate (12). An electrically conductive pattern (16) is formed on the substrate (12) and over the cavities (14). An electrically insulating layer (22) is formed over the substrate (12) and the electrically conductive pattern (16). A plurality of vias (24) is formed in the electrically insulating layer (22). An integrated circuit (IC) die (28) is attached to the electrically insulating layer (22) and electrically connected to the vias (24) such that the IC die (28) is connected to the electrically conductive pattern (16). A molding operation is performed to encapsulate the IC die (28). The substrate (12) is removed such that the electrically conductive pattern (16) is exposed.

Abstract: A semiconductor package and method of forming the package, including a substrate having an opening formed therein. Contact pads are formed about a periphery of the opening on a first side of the substrate and a second opposing side of the substrate. A flip chip die is mounted to the substrate, having an active side mounted on a first side of the substrate and in electrical communication with at least some of the contact pads formed on the first side of the substrate. At least one wire bond die is mounted through the opening, with a non-active side mounted on the active side of the flip chip die. The wire bond die is in electrical communication with at least some of the plurality of contact pads formed on the second opposing side of the substrate.

Abstract: A method of packaging semiconductor integrated circuits, including the steps of providing a transfer film and forming a patterned, conductive layer on a surface of the transfer film. A first semiconductor integrated circuit (IC) then is attached to the transfer film, where an active side of the first IC is attached to the transfer film. A second semiconductor IC then is attached to the first IC, where a bottom side of the second IC is attached to a bottom side of the first IC. Die pads on an active surface of the second IC are electrically connected to the conductive layer with wires and then a resin material is provided on one side of the transfer film to encapsulate the first and second ICs, the wires and a portion of the conductive layer. Next the transfer film is removed, which exposes the active side of the first IC and the conductive layer.

Abstract: An array QFN package (10) includes a first semiconductor package (12) and a lead frame (14) having a plurality of leads (16). A first IC die (22) is attached on a first side to the first semiconductor package (12) and is electrically connected to the leads (16) of the lead frame (14). A mold compound (30) encapsulates the first IC die (22), a portion of the first semiconductor package (12) and a portion of the leads (16) such that a plurality of I/O terminals (32) on the semiconductor package (10) is exposed.

Abstract: A flip-chip bump carrier type package is formed by providing a sheet of metal foil and forming cavities in a first surface of the sheet. The cavities are plated with a conductive metal to form external interconnects. An insulating film is formed over the metal foil first surface and the plated cavities and then vias are formed in the insulating film. The vias contact respective ones of the plated cavities. The vias are then plated and a solder resist film is formed over the insulating film and the plated vias. The solder resist film is processed to form exposed areas above the vias, which areas are then plated with a conductive metal. A bumped semiconductor die is attached to the first surface of the metal foil, where the die bumps contact respective ones of the plated, exposed areas, which electrically connects the die to the plated cavities. Finally, the sheet of metal foil is removed so that outer surfaces of the plated cavities are exposed.

Abstract: A method of attaching a capacitor (112) to a substrate (100) includes applying a flux (108) to respective capacitor pads (104, 106) on the substrate (100). The capacitor (112) is placed on the fluxed capacitor pads (104, 106) and a reflow operation is performed on the capacitor (112) and the substrate (100) such that intermetallic interconnects (128) are formed between the capacitor (112) and the substrate (100).

Abstract: A method of manufacturing a semiconductor wafer for dicing includes providing a semiconductor wafer including a substrate and a plurality of upper layers on the substrate that form a formation of die areas. The formation is arranged so that adjacent die areas are separated by a path for a dicing tool within each path, a pair of spaced apart lines is fabricated. Each line defines a dicing edge of a respective path and has at least one trench extending between a top surface of the wafer and the substrate. Each trench is filled with a stress absorbing material for reducing die tool induced stress on the die areas during dicing.

Abstract: A method of making a stacked die package (39) includes placing a first flip chip die (16) on a base carrier (12) and electrically connecting the first flip chip die (16) to the base carrier (12). A second flip chip die (18) is attached back-to-back to the first flip chip die (16) and electrically connected to the base carrier (12) with a plurality of insulated wires (20). A mold compound (36) is formed over the first and second dice and one surface of the base carrier.

Abstract: A semiconductor package (100, 150, 200, 250), and method of forming the package, including a substrate (102, 102?, 202, 202?) having an opening (104, 104?, 204, 204?) formed therein. Contact pads (112, 112?, 212, 212?) are formed about a periphery of the opening on a first side of the substrate (106, 106?, 206, 206?) and a second opposing side (132, 132?, 232, 232?) of the substrate. A flip chip die (120, 120?, 220, 220?) is mounted to the substrate, having an active side (114, 114?, 214, 214?) mounted on a first side of the substrate and in electrical communication with at least some of the contact pads formed on the first side of the substrate. At least one wire bond die (110, 110?, 210, 210?) is mounted through the opening, with a non-active side mounted on the active side of the flip chip die. The wire bond die is in electrical communication with at least some of the plurality of contact pads formed on the second opposing side of the substrate.

Abstract: An array QFN package (10) includes a first semiconductor package (12) and a lead frame (14) having a plurality of leads (16). A first IC die (22) is attached on a first side to the first semiconductor package (12) and is electrically connected to the leads (16) of the lead frame (14). A mold compound (30) encapsulates the first IC die (22), a portion of the first semiconductor package (12) and a portion of the leads (16) such that a plurality of I/O terminals (32) on the semiconductor package (10) is exposed.

Abstract: A method of forming a semiconductor packaged device (10) including die bonding a flip chip die (12) to a first surface (14) of a lead frame (28). A lid (34) is attached to a top surface (36) of the flip chip die (12). A wire bond die (40) is attached to a second surface (22) of the lead frame (28) and electrically connected to the lead frame (28) with wires (44). A mold compound then is formed over the flip chip die (12), the wire bond die (40) and the lead frame (28).

Abstract: A stacked multichip package (100) has a base carrier (102) having a top side (108) and a bottom side (110), a bottom integrated circuit die (104) having a bottom surface (112) attached to the base carrier top side (108), and an opposing, top surface (114). The top surface (114) has a peripheral area including a plurality of first bonding pads and a central area (120). A bead (124) is formed on the top surface (114) of the bottom die (104) between the peripheral area and the central area (120). A top integrated circuit die (106) having a bottom surface is positioned over the bottom die (104) and the bottom surface of the top die (106) is attached to the top surface (114) of the bottom die (104) via the bead (124). The bead (124) maintains a predetermined spacing between the bottom die (104) and the top die (106) so that wirebonds of first wires (122) connecting the bottom die (104) to the base carrier (102) are not damaged when the top die (106) is attached to the bottom die (104).

Abstract: A method of making a stacked die package (50) includes attaching and electrically connecting a first integrated circuit (IC) die (52) to a base carrier (56). A plurality of successive layers (54A, 54B and 54C) of an adhesive material (54) is formed on the first die (52). A second die (72) is attached to the first die (52) with the adhesive material (54) such that the successive layers of adhesive material (54A, 54B and 54C) maintain a predetermined spacing (H) between the first die (52) and the second die (72). The second die (72) is electrically connected to the base carrier (56).