Patents by Inventor Walter E. Donovan
Walter E. Donovan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120084334Abstract: Methods and systems for decompressing data are described. The relative magnitudes of a first value and a second value are compared. The first value and the second value represent respective endpoints of a range of values. The first value and the second value each have N bits of precision. Either the first or second value is selected, based on the result of the comparison. The selected value is scaled to produce a third value having N+1 bits of precision. A specified bit value is appended as the least significant bit of the other (non-selected) value to produce a fourth value having N+1 bits of precision.Type: ApplicationFiled: December 13, 2011Publication date: April 5, 2012Applicant: NVIDIA CORPORATIONInventors: Douglas H. Rogers, Gary C. King, Walter E. Donovan
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Patent number: 8098257Abstract: Floating-point texture filtering units leverage existing fixed-point filter circuits. Groups of floating-point texture values are converted to products of a fixed-point mantissa and a scaling factor that is the same for each texture value in the group. The fixed-point mantissas are filtered using a fixed-point filter circuit, and the filtered mantissa is combined with the scaling factor to determine a floating-point filtered value. Multiple floating-point filter results may be combined in a floating-point accumulator circuit. The same fixed-point filter circuit may also be used to filter fixed-point texture data by providing fixed-point input path that bypasses the format conversion and a fixed-point accumulator.Type: GrantFiled: February 15, 2008Date of Patent: January 17, 2012Assignee: NVIDIA CorporationInventors: Walter E. Donovan, Anders M. Kugler, Christopher D. S. Donham
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Patent number: 8078656Abstract: Methods and systems for decompressing data are described. The relative magnitudes of a first value and a second value are compared. The first value and the second value represent respective endpoints of a range of values. The first value and the second value each have N bits of precision. Either the first or second value is selected, based on the result of the comparison. The selected value is scaled to produce a third value having N+1 bits of precision. A specified bit value is appended as the least significant bit of the other (non-selected) value to produce a fourth value having N+1 bits of precision.Type: GrantFiled: November 16, 2004Date of Patent: December 13, 2011Assignee: NVIDIA CorporationInventors: Douglas H. Rogers, Gary C. King, Walter E. Donovan
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Patent number: 8065354Abstract: Systems and methods compress and decompress 16 bit data. The 16 bit data may be signed or unsigned and represented in a fixed point or floating point format. A fixed block size of data is compressed into a fixed length format. Data compressed using a medium quality compression scheme may be efficiently decompressed in hardware. Data may be efficiently compressed and decompressed in hardware using a high quality compression scheme. The high quality compression scheme has a lower compression ratio compared with the medium quality compression scheme, but is near lossless in terms of quality.Type: GrantFiled: April 27, 2005Date of Patent: November 22, 2011Assignee: NVIDIA CorporationInventors: Walter E. Donovan, David K. McAllister
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Patent number: 8023752Abstract: Systems and methods compress and decompress 16 bit data. The 16 bit data may be signed or unsigned and represented in a fixed point or floating point format. A fixed block size of data is compressed into a fixed length format. Data compressed using a medium quality compression scheme may be efficiently decompressed in hardware. Data may be efficiently compressed and decompressed in hardware using a high quality compression scheme. The high quality compression scheme has a lower compression ratio compared with the medium quality compression scheme, but is near lossless in terms of quality.Type: GrantFiled: April 27, 2005Date of Patent: September 20, 2011Assignee: NVIDIA CorporationInventors: Walter E. Donovan, David K. McAllister
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Patent number: 7982745Abstract: Trilinear optimization is a technique to reduce the number of texture samples used to determine a texture value associated with a graphics fragment. Bilinear interpolations replace some trilinear interpolations, thereby reducing the number of texture samples read and simplifying the filter computation. A programmable trilinear slope is used to control replacement of a trilinear computation with a bilinear computation, permitting a user to determine a balance between improved texture map performance and texture filtering quality.Type: GrantFiled: December 13, 2007Date of Patent: July 19, 2011Assignee: NVIDIA CorporationInventors: Walter E. Donovan, Paul S. Heckbert
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Patent number: 7983498Abstract: Systems and methods for representing low dynamic range data in compressed formats with a fixed size block allow low dynamic range data to be stored in less memory. The compressed formats use 8 bits per pixel to represent 24 bits of low dynamic range data for each pixel. The compressed format includes four or six endpoint values, a partition index that specifies a mask for each pair of the endpoint values, and an index for each pixel in the block. The indices are compressed to allow more bits for the endpoint values. Mode bits are included to distinguish between the different encodings and various blocks within a single compressed image may be encoded differently. Compressed low dynamic range values may be efficiently decompressed in hardware.Type: GrantFiled: August 6, 2007Date of Patent: July 19, 2011Assignee: NVIDIA CorporationInventor: Walter E. Donovan
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Publication number: 20110169850Abstract: A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.Type: ApplicationFiled: March 28, 2011Publication date: July 14, 2011Applicant: NVIDIA CORPORATIONInventors: Walter E. Donovan, Emmett M. Kilgariff, Karim M. Abdalla, Joel J. McCormack
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Patent number: 7978921Abstract: Systems and methods for representing low dynamic range data in compressed formats with a fixed size block allow low dynamic range data to be stored in less memory. The compressed formats use 8 bits per pixel to represent 24 bits of low dynamic range data for each pixel. The compressed format includes four or six endpoint values, a partition index that specifies a mask for each pair of the endpoint values, and an index for each pixel in the block. The indices are compressed to allow more bits for the endpoint values. Mode bits are included to distinguish between the different encodings and various blocks within a single compressed image may be encoded differently. Compressed low dynamic range values may be efficiently decompressed in hardware.Type: GrantFiled: August 6, 2007Date of Patent: July 12, 2011Assignee: NVIDIA CorporationInventor: Walter E. Donovan
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Patent number: 7961195Abstract: Methods and systems for compressing and decompressing data are described. A first value of N+1 bits and a second value of N+1 bits are reduced to strings of N bits each. The first and second strings of N bits are stored in a particular order relative to one another in a compression block. The particular order in which the first and second strings of N bits are stored in the compression block is used to derive a bit value that is then used in combination with one of the strings of N bits to reconstruct that string as N+1 bits.Type: GrantFiled: November 16, 2004Date of Patent: June 14, 2011Assignee: Nvidia CorporationInventors: Douglas H. Rogers, Gary C. King, Walter E. Donovan
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Publication number: 20110090251Abstract: One embodiment of the present invention sets forth a technique for converting alpha values into pixel coverage masks. Geometric coverage is sampled at a number of “real” sample positions within each pixel. Color and depth values are computed for each of these real samples. Fragment alpha values are used to determine an alpha coverage mask for the real samples and additional “virtual” samples, in which the number of bits set in the mask bits is proportional to the alpha value. An alpha-to-coverage mode uses the virtual samples to increase the number of transparency levels for each pixel compared with using only real samples. The alpha-to-coverage mode may be used in conjunction with virtual coverage anti-aliasing to provide higher-quality transparency for rendering anti-aliased images.Type: ApplicationFiled: October 14, 2010Publication date: April 21, 2011Inventors: Walter E. Donovan, Emmett M. Kilgariff, Steven E. Molnar, Christian Amsinck, Robert Ohannessian
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Publication number: 20110090250Abstract: One embodiment of the present invention sets forth a technique for converting alpha values into pixel coverage masks. Geometric coverage is sampled at a number of “real” sample positions within each pixel. Color and depth values are computed for each of these real samples. Fragment alpha values are used to determine an alpha coverage mask for the real samples and additional “virtual” samples, in which the number of bits set in the mask bits is proportional to the alpha value. An alpha-to-coverage mode uses the virtual samples to increase the number of transparency levels for each pixel compared with using only real samples. The alpha-to-coverage mode may be used in conjunction with virtual coverage anti-aliasing to provide higher-quality transparency for rendering anti-aliased images.Type: ApplicationFiled: October 14, 2010Publication date: April 21, 2011Inventors: Steven E. MOLNAR, Emmett M. KILGARIFF, Walter E. DONOVAN, Christian AMSINCK, Robert OHANNESSIAN
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Patent number: 7920749Abstract: Systems and methods for representing high dynamic range data in compressed formats with a fixed size block allow high dynamic range data to be stored in less memory. The compressed formats use 8 bits per pixel. A first compressed format includes two endpoint values and compressed indices for the pixels in the block. A second compressed format includes four endpoint values, a partition index that specifies a mask for each pair of the four endpoint values, and compressed indices for the pixels in the block. The two formats may be used for various blocks within a single compressed image and mode bits are included to distinguish between the two formats. Furthermore, each endpoint value may be encoded using an endpoint compression mode that is also specified by the mode bits. Compressed high dynamic range values represented in either format may be efficiently decompressed in hardware.Type: GrantFiled: September 17, 2007Date of Patent: April 5, 2011Assignee: NVIDIA CorporationInventor: Walter E. Donovan
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Patent number: 7916149Abstract: A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size of the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.Type: GrantFiled: January 4, 2005Date of Patent: March 29, 2011Assignee: NVIDIA CorporationInventors: Walter E. Donovan, Emmett M. Kilgariff, Karim M. Abdalla, Joel J. McCormack
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Patent number: 7852346Abstract: A programmable graphics processor including an execution pipeline and a texture unit is described. The execution pipeline processes graphics data as specified by a fragment program. The fragment program may include one or more opcodes. The texture unit includes one or more sub-units which execute the opcodes to perform specific operations such as an LOD computation, generation of sample locations used to read texture map data, and address computation based on the sample locations.Type: GrantFiled: November 22, 2005Date of Patent: December 14, 2010Assignee: NVIDIA CorporationInventors: Walter E. Donovan, John Erik Lindholm
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Patent number: 7742646Abstract: Systems and methods for representing high dynamic range data in compressed formats with a fixed size block allow high dynamic range data to be stored in less memory. The compressed formats use 8 bits per pixel. A first compressed format includes two endpoint values and an index for each pixel in the block. A second compressed format includes four endpoint values, a partition index that specifies a mask for each pair of the four endpoint values, and an index for each pixel in the block. The two formats may be used for various blocks within a single compressed image and mode bits are included to distinguish between the two formats. Furthermore, each endpoint value may be encoded using an endpoint compression mode that is also specified by the mode bits. Compressed high dynamic range values represented in either format may be efficiently decompressed in hardware.Type: GrantFiled: December 20, 2006Date of Patent: June 22, 2010Assignee: NVIDIA CorporationInventor: Walter E. Donovan
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Patent number: 7737988Abstract: Systems and methods used for font filtering may also be used to perform texture blits. Texture data is read in blocks that are coarsely aligned. Font engines may be used to align the texture data as specified by a copy (blit) instruction to provide a finely aligned region of the texture data within a font filter footprint. The finely aligned region is then bilinearly filtered using a “nearest” mode to provide the bit aligned region of the texture map specified by the copy instruction.Type: GrantFiled: November 14, 2005Date of Patent: June 15, 2010Assignee: NVIDIA CorporationInventors: Michael J. M. Toksvig, Alexander L. Minkin, Walter E. Donovan
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Patent number: 7626587Abstract: A computer system including a processor, a display, and a graphics unit coupled between the processor and the display, in which the processor is configured to perform multi-display operations which generate multiple frames of display data for simultaneous display, and a graphics unit for use in such a system. Typically, the graphics unit includes graphics memory that includes at least two frame buffers, and the processor operates as if it were independently asserting multiple streams of display data to multiple frame buffers for driving multiple displays independently. Another aspect of the invention is a system that displays data from a frame buffer on a screen.Type: GrantFiled: January 6, 2005Date of Patent: December 1, 2009Assignee: NVIDIA CorporationInventors: Abraham B. de Waal, Walter E. Donovan
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Patent number: 7623133Abstract: A computer system including a processor, a display, and a graphics unit coupled between the processor and the display, in which the processor is configured to perform multi-display operations which generate multiple frames of display data for simultaneous display, and a graphics unit for use in such a system. Typically, the graphics unit includes graphics memory that includes at least two frame buffers, and the processor operates as if it were independently asserting multiple streams of display data to multiple frame buffers for driving multiple displays independently. Another aspect of the invention is a system that displays data from a frame buffer on a screen.Type: GrantFiled: January 6, 2005Date of Patent: November 24, 2009Assignee: NVIDIA CorporationInventors: Abraham B. de Waal, Walter E. Donovan
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Patent number: 7620210Abstract: Anisotropic optimization is a technique to reduce the number of texture samples anisotropically filtered to determine a texture value associated with a graphics fragment. Reducing the number of texture samples anisotropically filtered reduces the number of texture samples read from memory and speeds up the filter computation. A programmable bias is used to control the number of texture samples used during anisotropic filtering, permitting a user to determine a balance between improved texture map performance and anisotropic texture filtering quality.Type: GrantFiled: January 16, 2008Date of Patent: November 17, 2009Assignee: NVIDIA CorporationInventors: Walter E. Donovan, Anders M. Kugler