Abstract: A substrate processing apparatus and a substrate processing method using plasma capable of controlling an etch rate and/or uniformity according to a position of a substrate are provided. The substrate processing apparatus includes a first space disposed between an electrode and an ion blocker; a second space disposed between the ion blocker and a shower head; a processing space for processing a substrate under the shower head; a first gas supply module for providing a first gas for generating plasma in the first space; a second gas supply module for providing a second gas to be mixed with the effluent of the plasma in the processing space; and a third gas supply module for providing a third gas to be mixed with the effluent of the plasma in the processing space.

Abstract: An apparatus for treating a substrate includes a process chamber having an inner space, a support unit supporting a substrate in the inner space, a processing gas supply unit for supplying a processing gas to the inner space, and a plasma source that excites the processing gas in a plasma state in the inner space. The processing gas supply unit includes a heater that heats the processing gas.

Abstract: A method for processing a substrate includes providing the substrate, a film being formed on the substrate, performing pretreatment to surface-treat the film formed on the substrate using a treatment gas in a plasma state, and performing, after the pretreatment, liquid treatment to remove the film from the substrate by supplying a treatment liquid onto the substrate.

Abstract: The present invention relates to a substrate processing apparatus capable of shortening a process time, and the substrate processing apparatus according to the present invention comprises an index chamber having a transfer robot loading/unloading a substrate; a process chamber having a heating means heating the substrate and processing the substrate; a loadlock chamber disposed between the index chamber and the process chamber; and a conveying chamber having a conveying robot conveying the substrate between the process chamber and the loadlock chamber, wherein a pre-heating means is provided in the conveying robot to pre-heat the substrate in a state before processing.

Abstract: An apparatus and method for processing a substrate using plasma, which has high plasma stability and process reproducibility, is provided. The method includes providing an apparatus for processing a substrate comprising a plasma generating region and a process region separate from the plasma generating region, placing the substrate including a silicon layer and an oxide layer in the process region, forming a hydrogen atmosphere in the process region by providing a hydrogen-based gas to the process region without passing through the plasma generating region, generating plasma by providing a fluorine-based gas to the plasma generating region, and providing the generated plasma to the process region to selectively remove the silicon layer compared to the oxide layer.

Abstract: Methods are disclosed that selectively deposit a protective material on the top regions of patterned photoresist layers, such patterned EUV photoresist layers, to provide a protective cap that reduces erosion damage during etch processes used for pattern transfer. Some deposition of the protective material on the sidewalls of the patterned photoresist layer is acceptable, and any deposition of the protective material on the underlying layer below the patterned photoresist layer is preferably thinner than the deposition at the top of the photoresist pattern. Further, the selective deposition of protective caps can be implemented, for example, through the application of high-rotation speeds to spatial atomic layer deposition (ALD) techniques. The selective deposition of protective caps increases the flexibility of options to improve etch resistance for various processes/materials.

Abstract: A patterned photo resist layer (for example an EUV photo resist layer), which may exhibit line width roughness (LWR) and line edge roughness (LER) or scum is treated with a plasma treatment before subsequent etching processes. The plasma treatment reduces LWR, LER, and/or photo resist scum. In one exemplary embodiment, the plasma treatment may include a plasma formed using a gas having a boron and halogen compound. In one embodiment, the gas compound may be a boron and chlorine compound, for example boron trichloride (BCl3) gas. In another embodiment, the gas compound may be a boron and fluorine compound, for example BxFy gases. The plasma treatment process may modify the photoresist surface to improve LWR, LER, and scum effects by removing roughness from the photo resist surface and removing photo resist residues which may case scumming.

Abstract: Methods are disclosed that selectively deposit a protective material on the top regions of patterned photoresist layers, such patterned EUV photoresist layers, to provide a protective cap that reduces erosion damage during etch processes used for pattern transfer. Some deposition of the protective material on the sidewalls of the patterned photoresist layer is acceptable, and any deposition of the protective material on the underlying layer below the patterned photoresist layer is preferably thinner than the deposition at the top of the photoresist pattern. Further, the selective deposition of protective caps can be implemented, for example, through the application of high-rotation speeds to spatial atomic layer deposition (ALD) techniques. The selective deposition of protective caps increases the flexibility of options to improve etch resistance for various processes/materials.

Abstract: Provided are an apparatus and a method of treating a substrate using process gas. The apparatus may include a chamber configured to provide a treatment space, in which a process of treating a substrate is performed, a detection unit configured to detect an amount of reaction by-products attached on an inner surface of the chamber. The detection unit may include a window member provided on the inner surface of the chamber, and a light source member configured to emit and receive light through the window member.

Abstract: Provided are an apparatus and a method of treating a substrate using process gas. The apparatus may include a chamber configured to provide a treatment space, in which a process of treating a substrate is performed, a detection unit configured to detect an amount of reaction by-products attached on an inner surface of the chamber. The detection unit may include a window member provided on the inner surface of the chamber, and a light source member configured to emit and receive light through the window member.

Abstract: Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates.

Abstract: Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

Abstract: Method of Fabricating Interconnections of a Microelectronic Device Using a Dual Damascene Process. A method of fabricating interconnections of a microelectronic device includes preparing a semiconductor substrate comprising a lower dielectric layer and a lower interconnection, forming an etch stopper layer and an interlayer dielectric layer on the semiconductor substrate, forming a via hole in the interlayer dielectric layer so that the etch stopper layer is exposed through the via hole, performing carbon doping on the etch stopper layer, performing trench etching to form a trench in the interlayer dielectric layer so that the trench overlaps part of the via hole, removing the carbon-doped etch stopper layer, and filling the via hole and the trench with a conductive material to form an upper interconnection.

Abstract: Methods of forming integrated circuit devices include steps to selectively widen portions of a mask pattern extending adjacent an outer edge of a semiconductor wafer. These steps to selectively widen portions of the mask pattern are performed so that more uniform center-to-edge critical dimensions (CD) can be achieved when the mask pattern is used to support photolithographically patterning of underlying layers (e.g., insulating layers, antireflective coatings, etc.).

Abstract: Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates.

Abstract: Methods of forming electrical interconnect structures include forming a dielectric layer on a semiconductor substrate and forming a hard mask layer on the dielectric layer. A photoresist layer is patterned on an upper surface of the hard mask layer. This patterned photoresist layer is used as an etching mask during a step to selectively etch the hard mask layer and define an opening therein. This opening exposes the first dielectric layer. The patterned photoresist layer is then stripped from the hard mask layer using an ashing process that exposes the upper surface of the hard mask layer. Following this ashing process, a portion of the first dielectric layer extending opposite the opening is selectively etched using the hard mask layer as an etching mask. During this selective etching step, polymer residues are accumulated directly on the upper surface of the hard mask layer.

Abstract: Methods of forming metal interconnect structures include forming a first electrically insulating layer on a semiconductor substrate and forming a second electrically insulating layer on the first electrically insulating layer. The second and first electrically insulating layers are selectively etched in sequence to define a contact hole therein. A first metal layer (e.g., tungsten) is deposited. This first metal layer extends on the second electrically insulating layer and into the contact hole. The first metal layer is then patterned to expose the second electrically insulating layer. The second electrically insulating layer is selectively etched for a sufficient duration to expose the first electrically insulating layer and expose a metal plug within the contact hole. This selective etching step is performed using the patterned first metal layer as an etching mask. A seam within the exposed metal plug is then filled with an electrically conductive filler material (e.g., CoWP).

Abstract: Methods of forming integrated circuit devices include steps to selectively widen portions of a mask pattern extending adjacent an outer edge of a semiconductor wafer. These steps to selectively widen portions of the mask pattern are performed so that more uniform center-to-edge critical dimensions (CD) can be achieved when the mask pattern is used to support photolithographically patterning of underlying layers (e.g., insulating layers, antireflective coatings, etc.).

Abstract: Method of Fabricating Interconnections of a Microelectronic Device Using a Dual Damascene Process. A method of fabricating interconnections of a microelectronic device includes preparing a semiconductor substrate comprising a lower dielectric layer and a lower interconnection, forming an etch stopper layer and an interlayer dielectric layer on the semiconductor substrate, forming a via hole in the interlayer dielectric layer so that the etch stopper layer is exposed through the via hole, performing carbon doping on the etch stopper layer, performing trench etching to form a trench in the interlayer dielectric layer so that the trench overlaps part of the via hole, removing the carbon-doped etch stopper layer, and filling the via hole and the trench with a conductive material to form an upper interconnection.

Abstract: Methods of forming electrical interconnect structures include forming a dielectric layer on a semiconductor substrate and forming a hard mask layer on the dielectric layer. A photoresist layer is patterned on an upper surface of the hard mask layer. This patterned photoresist layer is used as an etching mask during a step to selectively etch the hard mask layer and define an opening therein. This opening exposes the first dielectric layer. The patterned photoresist layer is then stripped from the hard mask layer using an ashing process that exposes the upper surface of the hard mask layer. Following this ashing process, a portion of the first dielectric layer extending opposite the opening is selectively etched using the hard mask layer as an etching mask. During this selective etching step, polymer residues are accumulated directly on the upper surface of the hard mask layer.