Abstract: A semiconductor device having a self-aligned contact is made by a method in which the conductive layer from which the contact is formed is substantially free of voids. A polysilicon layer mask pattern is formed on an interlayer insulating layer. The interlayer insulating layer is then subjected to a self-aligned contact etching process in which the polysilicon layer mask pattern is used as an etching mask. As a result, a contact hole is formed that exposes a portion of the semiconductor substrate. Next, protective layer spacers are formed at both side walls of the interlayer insulating layer and the mask pattern that define the contact hole. The exposed surface of the semiconductor substrate may then be cleaned. Subsequently, a conductive layer is formed to fill the contact hole. Accordingly, an undercut does not at the interface between the interlayer insulating layer pattern and the mask pattern during the cleaning process.

Abstract: A method of forming an interlevel dielectric layer of a semiconductor device includes filling the gap between conductive lines without the generation of voids or cracks. In the method of forming the interlevel dielectric layer of the semiconductor device, a conductive line is formed on a semiconductor substrate. A polysilazane-family SOG layer is deposited on the semiconductor substrate on which the conductive line is formed. The polysilazane-family SOG layer is baked and etched back until the upper part of the conductive line is exposed using a C—F-family gas having a high C to F ratio, resulting in high etch selectivity ratio of the SOG layer to a silicon nitride layer. A silicon oxide layer, serving as an interlevel dielectric layer, is formed by thermally treating the polysilazane-family SOG layer remaining after the etch back process.

Abstract: A self-aligned contact hole is formed in a cell area of a semiconductor device, and then a polysilicon layer is formed on both the cell area and a peripheral circuit area. A first etch back process is performed using a reactant etching gas, such as Cl2 gas, having a high etching rate with respect to the polysilicon layer. This first etch back process on the polysilicon layer is stopped before exposing the top surface of a capping layer in the peripheral circuit area, thereby leaving a thin polysilicon film on the capping layer. A second etch back process is then performed to form a polysilicon node filling the self-aligned contact hole in the cell area. In the second etch back process, an etching reactant gas, such as HBr gas, is used, which has a high etching selectivity of polysilicon with respect to the capping layer.