Abstract: Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

Abstract: Embodiments of the invention include a MIM capacitor having a high capacitance with improved manufacturability. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

Abstract: A method of fabricating dual damascene interconnections is provided. A dual damascene region is formed in a hybrid dielectric layer having a dielectric constant of 3.3 or less, and a carbon-free inorganic material is used as a via filler. The present invention improves electrical properties of dual damascene interconnections and minimizes defects.

Abstract: In a method for determining the degree of charge-up induced by plasma used for manufacturing a semiconductor device and an apparatus therefor, a predetermined region on a surface of a wafer on which a plasma process has been performed is repeatedly scanned with a primary electron beam. Secondary electrons generated by a reaction between the primary electron beam and the surface of the wafer that are emitted to the outside of the surface of the wafer are collected. The degree of charge-up induced at the surface of the wafer by the plasma used during the plasma process is determined from the change in the amount of collected secondary electrons. Determination as to whether a contact hole is opened or as to the degree of degradation of a gate insulating layer is made based on the degree of charge-up.

Abstract: A dual damascene process is disclosed. According to the dual damascene process of the present invention, a first recessed region through an intermetal dielectric layer is filled with a bottom protecting layer, and the bottom protecting layer and the intermetal dielectric layer are simultaneously etched to form a second recessed region that has a shallower depth and wider width than the first recessed region on the first recessed region by using an etch gas selectively etches the intermetal dielectric layer with respect to the bottom protecting layer. In other words, the etch selectivity ratio, the intermetal dielectric layer with respect to the bottom protecting layer, is preferably about 0.5 to about 1.5. Thus, it is possible to form a dual damascene structure without the formation of a byproduct or an oxide fence.

Abstract: A dry etching method comprises placing a semiconductor substrate in a reactor, the semiconductor substrate comprising a photoresist pattern formed on an etching target layer, supplying carbon monoxide gas into the reactor to selectively deposit polymer on the photoresist pattern to form a polymer layer, and etching the etching target layer using the photoresist pattern and the polymer layer as an etch mask.

Abstract: In a method for forming a dual damascene wiring pattern, an etch stop film and an interlayer dielectric film comprising an SiOC:H group material are formed on a substrate having an electrical connection layer formed thereon. An anti-reflection layer is formed on the interlayer dielectric film. A primary opening is formed by etching the anti-reflection layer and the interlayer dielectric film to expose a surface of the etch stop film. A sacrificial film is formed comprising a low dielectric constant material in the primary opening and on the anti-reflection layer. A trench photoresist pattern having a width larger than that of the primary opening is formed on the sacrificial film after plasma-processing the sacrificial film.

Abstract: Provided are an inter-metal dielectric pattern and a method of forming the same. The pattern includes a lower interconnection disposed on a semiconductor substrate, a lower dielectric layer having a via hole exposing the lower interconnection and covering the semiconductor substrate where the lower interconnection is disposed, and an upper dielectric pattern and a lower capping pattern, which include a trench line exposing the via hole and sequentially stacked on the lower dielectric layer. The lower dielectric layer and the upper dielectric pattern are low k-dielectric layers formed of materials such as SiO2, SiOF, SiOC, and porous dielectric. The method includes forming an inter-metal dielectric layer including a lower dielectric layer and upper dielectric layer, which are sequentially stacked, on a lower interconnection formed on a semiconductor substrate. The inter-metal dielectric layer is patterned to form a via hole, which exposes the upper side of the lower interconnection.

Abstract: A method and apparatus for use in manufacturing a semiconductor device strips a polysilicon hard mask without damaging the layer left exposed by openings formed by using the polysilicon hard mask as an etching mask. The method includes forming a polysilicon hard mask in a pattern on a first layer to expose a portion of the first layer, dry etching the exposed portion of the first layer using the polysilicon hard mask as an etching mask to form an opening in the first layer, and thereafter removing the polysilicon hard mask by supplying an etching gas onto the polysilicon hard mask in a direction parallel to the major surface of the semiconductor substrate.

Abstract: Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

Abstract: A method of fabricating dual damascene interconnections is provided. A dual damascene region is formed in a hybrid dielectric layer having a dielectric constant of 3.3 or less, and a carbon-free inorganic material is used as a via filler. The present invention improves electrical properties of dual damascene interconnections and minimizes defects.

Abstract: A method and apparatus for use in manufacturing a semiconductor device strips a polysilicon hard mask without damaging the layer left exposed by openings formed by using the polysilicon hard mask as an etching mask. The method includes forming a polysilicon hard mask in a pattern on a first layer to expose a portion of the first layer, dry etching the exposed portion of the first layer using the polysilicon hard mask as an etching mask to form an opening in the first layer, and thereafter removing the polysilicon hard mask by supplying an etching gas onto the polysilicon hard mask in a direction parallel to the major surface of the semiconductor substrate.

Abstract: In a method for determining the degree of charge-up induced by plasma used for manufacturing a semiconductor device and an apparatus therefor, a predetermined region on a surface of a wafer on which a plasma process has been performed is repeatedly scanned with a primary electron beam. Secondary electrons generated by a reaction between the primary electron beam and the surface of the wafer that are emitted to the outside of the surface of the wafer are collected. The degree of charge-up induced at the surface of the wafer by the plasma used during the plasma process is determined from the change in the amount of collected secondary electrons. Determination as to whether a contact hole is opened or as to the degree of degradation of a gate insulating layer is made based on the degree of charge-up.

Abstract: A dual damascene process is disclosed. According to the dual damascene process of the present invention, a first recessed region through an intermetal dielectric layer is filled with a bottom protecting layer, and the bottom protecting layer and the intermetal dielectric layer are simultaneously etched to form a second recessed region that has a shallower depth and wider width than the first recessed region on the first recessed region by using an etch gas selectively etches the intermetal dielectric layer with respect to the bottom protecting layer. In other words, the etch selectivity ratio, the intermetal dielectric layer with respect to the bottom protecting layer, is preferably about 0.5 to about 1.5. Thus, it is possible to form a dual damascene structure without the formation of a byproduct or an oxide fence.

Abstract: In a method for forming a dual damascene wiring pattern, an etch stop film and an interlayer dielectric film comprising an SiOC:H group material are formed on a substrate having an electrical connection layer formed thereon. An anti-reflection layer Is formed on the interlayer dielectric film. A primary opening s formed by etching the anti-reflection layer and the interlayer dielectric film to expose a surface of the etch stop film. A sacrificial film is formed comprising a low dielectric constant material in the primary opening and on the anti-reflection layer. A trench photoresist pattern having a width larger than that of the primary opening is formed on the sacrificial film after plasma-processing the sacrificial film.

Abstract: In a method for determining the degree of charge-up induced by plasma used for manufacturing a semiconductor device and an apparatus therefor, a predetermined region on a surface of a wafer on which a plasma process has been performed is repeatedly scanned with a primary electron beam. Secondary electrons generated by a reaction between the primary electron beam and the surface of the wafer that are emitted to the outside of the surface of the wafer are collected. The degree of charge-up induced at the surface of the wafer by the plasma used during the plasma process is determined from the change in the amount of collected secondary electrons. Determination as to whether a contact hole is opened or as to the degree of degradation of a gate insulating layer is made based on the degree of charge-up.

Abstract: Provided are an inter-metal dielectric pattern and a method of forming the same. The pattern includes a lower interconnection disposed on a semiconductor substrate, a lower dielectric layer having a via hole exposing the lower interconnection and covering the semiconductor substrate where the lower interconnection is disposed, and an upper dielectric pattern and a lower capping pattern, which include a trench line exposing the via hole and sequentially stacked on the lower dielectric layer. The lower dielectric layer and the upper dielectric pattern are low k-dielectric layers formed of materials such as SiO2, SiOF, SiOC, and porous dielectric. The method includes forming an inter-metal dielectric layer including a lower dielectric layer and upper dielectric layer, which are sequentially stacked, on a lower interconnection formed on a semiconductor substrate. The inter-metal dielectric layer is patterned to form a via hole, which exposes the upper side of the lower interconnection.

Abstract: A method of forming an interlevel dielectric layer of a semiconductor device includes filling the gap between conductive lines without the generation of voids or cracks. In the method of forming the interlevel dielectric layer of the semiconductor device, a conductive line is formed on a semiconductor substrate. A polysilazane-family SOG layer is deposited on the semiconductor substrate on which the conductive line is formed. The polysilazane-family SOG layer is baked and etched back until the upper part of the conductive line is exposed using a C-F-family gas having a high C to F ratio, resulting in high etch selectivity ratio of the SOG layer to a silicon nitride layer. A silicon oxide layer, serving as an interlevel dielectric layer, is formed by thermally treating the polysilazane-family SOG layer remaining after the etch back process.

Abstract: A conducting line of a semiconductor device using an aluminum oxide layer as a hard mask, and a method of forming the conducting line. The conducting line, such as a gate line or a bit line of a semiconductor device, includes a conductive layer formed on a semiconductor substrate, a capping insulation layer formed on the conductive layer, and an aluminum oxide layer formed on the capping insulation layer, with the aluminum oxide layer being used as a hard mask.

Abstract: A conducting line of a semiconductor device using an aluminum oxide layer as a hard mask, and a method of forming the conducting line. The conducting line, such as a gate line or a bit line of a semiconductor device, includes a conductive layer formed on a semiconductor substrate, a capping insulation layer formed on the conductive layer, and an aluminum oxide layer formed on the capping insulation layer, with the aluminum oxide layer being used as a hard mask.