Abstract: Proposed is a layer structure (1100, 1030) comprising a crystalline piezoelectric III-N layer (1110, 1032) epitaxially grown over a metal layer which is epitaxially grown over a rare earth oxide layer on a semiconductor (1102, 1002). The rare earth oxide layer includes at least two discrete portions (1104, 1004), and the metal layer includes at least one metal portion (1108, 1006) that partially overlaps adjacent discrete portions, preferably forming a bridge over an air gap (1008), particularly suitable for RF filters.

Abstract: Proposed is a layer structure (1100, 1030) comprising a crystalline piezoelectric III-N layer (1110, 1032) epitaxially grown over a metal layer which is epitaxially grown over a rare earth oxide layer on a semiconductor (1102, 1002). The rare earth oxide layer includes at least two discrete portions (1104, 1004), and the metal layer includes at least one metal portion (1108, 1006) that partially overlaps adjacent discrete portions, preferably forming a bridge over an air gap (1008), particularly suitable for RF filters.

Abstract: A method of fabricating a composite semiconductor component comprising: (i) providing a bowed substrate comprising a wafer of synthetic diamond material having a thickness td, the bowed substrate being bowed by an amount B and comprising a convex face and a concave face; (ii) growing a layer of compound semiconductor material on the convex face of the bowed substrate via a chemical vapour deposition technique at a growth temperature T to form a bowed composite semiconductor component comprising the layer of compound semiconductor material of thickness tsc on the convex face of the bowed substrate, the compound semiconductor material having a higher average thermal expansion coefficient than the synthetic diamond material between the growth temperature T and room temperature providing a thermal expansion mismatch ?Tec; and (iii) cooling the bowed composite semiconductor component, wherein the layer of compound semiconductor material contracts more than the wafer of synthetic diamond material during cooling due

Abstract: A method of fabricating a composite semiconductor component comprising: (i) providing a bowed substrate comprising a wafer of synthetic diamond material having a thickness td, the bowed substrate being bowed by an amount B and comprising a convex face and a concave face; (ii) growing a layer of compound semiconductor material on the convex face of the bowed substrate via a chemical vapour deposition technique at a growth temperature T to form a bowed composite semiconductor component comprising the layer of compound semiconductor material of thickness tsc on the convex face of the bowed substrate, the compound semiconductor material having a higher average thermal expansion coefficient than the synthetic diamond material between the growth temperature T and room temperature providing a thermal expansion mismatch ?Tec; and (iii) cooling the bowed composite semiconductor component, wherein the layer of compound semiconductor material contracts more than the wafer of synthetic diamond material during cooling due

Abstract: A method of producing a template material for growing semiconductor materials and/or devices, comprises the steps of: (a) providing a substrate with a dielectric layer on the substrate; and (b) forming a pixelated pattern on the dielectric layer, the pattern comprising a plurality of discrete groups of structures.

Abstract: A method of producing a bulk semiconductor material comprises the steps of providing a base comprising a substantially planar substrate having a plurality of etched nano/micro-structures located thereon, each structure having an etched, substantially planar sidewall, wherein the plane of each said etched sidewall is arranged at an oblique angle to the substrate, and selectively growing the bulk semiconductor material onto the etched sidewall of each nano/micro-structure using an epitaxial growth process. A layered semiconductor device may be grown onto the bulk semiconductor material.

Abstract: A method for producing gallium nitride material, comprising the steps of: a) providing a substrate and forming a metal layer over the substrate; b) forming a transition layer over the metal layer, the transition layer being compositionally graded such that the composition of the transition layer at a depth (z) thereof is an Al concentration function f(z) of that depth; and c) forming a layer of gallium nitride material over the transition layer; wherein the Al compositional grading function f(z) of the transition layer grown in step b) has a profile including two plateaux at respective depths z1 and z2 where df(z1)/dz=df(z2)/dz=0, wherein the function decreases continuously between z1 and z2 with z2>z1.

Abstract: A method of producing single-crystal semiconductor material comprises: providing a template material; creating a mask on top of the template material; using the mask to form a plurality of nanostructures in the template material; and growing the single-crystal semiconductor material onto the nanostructures.

Abstract: A method of producing a template material for growing semiconductor materials and/or devices, comprises the steps of: (a) providing a substrate with a dielectric layer on the substrate; and (b) forming a pixelated pattern on the dielectric layer, the pattern comprising a plurality of discrete groups of structures.

Abstract: A method for growing flat, low defect density, and strain-free thick non-polar III-V nitride materials and devices on any suitable foreign substrates using a fabricated nanocolumns compliant layer with an HVPE growth process is provided. The method uses a combination of dry and wet etching to create nanocolumns consisting of layers of non-polar III nitride material and other insulating materials or materials used to grow the non-polar III-V nitride materials.

Abstract: A method of producing a layered semiconductor device comprises the steps of: (a) providing a base comprising a plurality of semiconductor nano-structures, (b) growing a semiconductor material onto the nano-structures using an epitaxial 5 growth process, and (c) growing a layer of the semiconductor material using an epitaxial growth process.

Abstract: A method for growing flat, low defect density, and strain-free thick non-polar III-V nitride materials and devices on any suitable foreign substrates using a fabricated nano-pores and nano-network compliant layer with an HVPE, MOCVD, and integrated HVPE/MOCVD growth process in a manner that minimum growth will occur in the nano-pores is provided. The method produces nano-networks made of the non-polar III-V nitride material and the substrate used to grow it where the network is continuous along the surface of the template, and where the nano-pores can be of any shape.

Abstract: A high fill factor textured light emitting diode structure comprises: a first textured cladding and contact layer (2) comprising a doped III-V or II-VI group compound semiconductor or alloys of such semiconductors deposited by epitaxial lateral overgrowth (ELOG) onto a patterned substrate (1); a textured undoped or doped active layer (3) comprising a III-V or II-VI group semiconductor or alloys of such semiconductors and where radiative recombination of electrons aid holes occurs or intersubband transition occurs; and a second textured cladding and contact layer (4) comprising a doped III-V or II-VI group semiconductor or alloys of such semiconductors.

Abstract: Deposited layers are advantageously obtained by utilizing a specific hydride vapor phase epitaxy deposition procedure. In this procedure, a vertical growth cell structure with extended diffusion layer, a homogenising diaphragm, sidewall purging gases, anal independent gas and substrate heaters is used for the deposition of III-V and VI compound semiconductors. This gas flow is uniformly mixed through the extended diffusion layer and directed so that it contacts the full surface of the substrate to produce high quality and uniform films. Exemplary of such gas flow configurations are the positioning of a substrate at a distance from the gas outlets to allow the extended diffusion and a diaphragm placed in a short distance above the substrate to minimize the impact of the convection effect and to improve the uniformity. This symmetrical configuration allows easy scale up from a single wafer to multi-wafer system.

Abstract: The present invention relates to a method of fabricating a high power light-emitting device using an electrolessly or electrolytically plated metal composite heat dissipation substrate having a high thermal conductivity and a thermal expansion coefficient matching with the device.

Abstract: A method of producing a layered semiconductor device comprises the steps of: (a) providing a base comprising a plurality of semiconductor nano-structures, (b) growing a semiconductor material onto the nano-structures using an epitaxial 5 growth process, and (c) growing a layer of the semiconductor material using an epitaxial growth process.

Abstract: A method utilizes HVPE to grow high quality flat and thick compound semiconductors (15) onto foreign substrates (10) using nanostructure compliant layers. Nanostructures (12) of semiconductor materials car be grown on foreign substrates (10) by molecular beam epitaxy (MBE), chemical vapour deposition (CVD), metalorganic chemical vapour deposition (MOCVD) and hydride vapour phase epitaxy (HVPE). Further growth of continuous compound semiconductor thick films (15) or wafer is achieved by epitaxial lateral overgrowth using HVPE.

Abstract: A method of producing single-crystal semiconductor material comprises: providing a template material; creating a mask on top of the template material; using the mask to form a plurality of nanostructures in the template material; and growing the single-crystal semiconductor material onto the nanostructures.

Abstract: A high fill factor textured light emitting diode structure comprises: a first textured cladding and contact layer (2) comprising a doped III-V or II-VI group compound semiconductor or alloys of such semiconductors deposited by epitaxial lateral overgrowth (ELOG) onto a patterned substrate (1); a textured undoped or doped active layer (3) comprising a III-V or II-VI group semiconductor or alloys of such semiconductors and where radiative recombination of electrons aid holes occurs or intersubband transition occurs; and a second textured cladding and contact layer (4) comprising a doped III-V or II-VI group semiconductor or alloys of such semiconductors.

Abstract: The present invention relates to a method of fabricating a high power light-emitting device using an electrolessly or electrolytically plated metal composite heat dissipation substrate having a high thermal conductivity and a thermal expansion coefficient matching with the device.