Abstract: A read bias scheme may be used for phase change memories including a chalcogenide access device and a chalcogenide memory element. Through an appropriate read bias scheme, desirable read margin can be achieved. This may result in better yield, higher reliability, and ultimately lower costs in some cases.

Abstract: A phase change memory may be read so as to reduce the likelihood of a read disturb. A read disturb may occur, for example, when a reset device is raised to a voltage, which causes its threshold device to trigger. The triggering of the threshold device produces a displacement current which may convert a reset device to a set device. By ensuring that the reset cell never reaches a voltage that would result in triggering of the threshold device, read disturbs may be reduced.

Abstract: A memory includes a storage element (OUM) made of a phase-change material for storing a logic value and an access element (OTS) switching from a higher resistance condition to a lower resistance condition in response to a selection of the memory cell, the access element in the higher resistance condition decoupling the storage element from a read circuit and in the lower resistance condition coupling the storage element to the read circuit. The read circuit includes a sense amplifier to determine the logic value stored in the memory cell according to an electrical quantity associated with the memory cell. The read circuit further includes a detector that detects the switching of the access element by comparison to a delayed waveform or sensing a change in the column rate of change, and a circuit to enable the sense amplifier in response to the detection of the switching of the access element.

Abstract: A memory may include a phase change memory element and series connected first and second selection devices. The second selection device may have a higher resistance and a larger threshold voltage than the first selection device. In one embodiment, the first selection device may have a threshold voltage substantially equal to its holding voltage. In some embodiments, the selection devices and the memory element may be made of chalcogenide. In some embodiments, the selection devices may be made of non-programmable chalcogenide. The selection device with the higher threshold voltage may contribute lower leakage to the combination, but may also exhibit increased snapback. This increased snapback may be counteracted by the selection device with the lower threshold voltage, resulting in a combination with low leakage and high performance in some embodiments.

Abstract: Briefly, in accordance with an embodiment of the invention, a method and system to program a memory material is provided. The method may include applying three signals having different durations and different amplitudes to a memory material to program the memory material to a predetermined state.

Abstract: Briefly, in accordance with an embodiment of the invention, a memory is provided. The memory may include a memory element and a first access device coupled to the memory element, wherein the first access device comprises a first chalcogenide material. The memory may further include a second access device coupled to the first access device, wherein the second access device comprises a second chalcogenide material.

Abstract: Briefly, in accordance with an embodiment of the invention, an apparatus and method to provide refreshing of a memory cell of a phase change memory device is provided. The method includes determining whether a storage level of a phase change memory cell is within a predetermined margin from a resistance threshold. In response to the determination, the cell is selectively written. The apparatus includes a circuit to: determine whether a storage level of a phase change memory cell is within a predefined margin from a resistance threshold level; and in response to the determination, selectively write to the cell.

Abstract: Briefly, in accordance with an embodiment of the invention, a memory is provided. The memory may include a memory element and a first access device coupled to the memory element, wherein the first access device comprises a first chalcogenide material. The memory may further include a second access device coupled to the first access device, wherein the second access device comprises a second chalcogenide material.

Abstract: Briefly, in accordance with an embodiment of the invention, a method and system to program a memory material is provided. The method may include applying three signals having different durations and different amplitudes to a memory material to program the memory material to a predetermined state.

Abstract: A semiconductor device system for coupling with external circuitry. The system includes a control signal on a carrier substrate. A semiconductor device is attached to the carrier substrate with an impedance matching device coupled to the control signal.

Abstract: A technique includes determining whether a storage level of a phase change memory cell is within a predefined margin from a resistance threshold. In response to the determination, the cell is selectively written.

Abstract: A semiconductor device system for coupling with external circuitry. The system includes a control signal on a carrier substrate. A semiconductor device is attached to the carrier substrate with an impedance matching device coupled to the control signal.

Abstract: A technique includes, in response to a request to write data to memory cells of a phase change memory device, placing the memory cells in a state that is shared in common among the memory cells. Also, in response to this request, the data is written to the memory cells.

Abstract: A technique includes, in response to a request to write data to memory cells of a phase change memory device, placing the memory cells in a state that is shared in common among the memory cells. Also, in response to this request, the data is written to the memory cells.

Abstract: An extensive network of N-channel transistor formed capacitor, with one node tie directly to VCC power bus and the other node directly VSS power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 &mgr;F.

Abstract: An extensive network of N-channel transistor formed capacitor, with one node tie directly to Vcc power bus and the other node directly Vss power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 &mgr;F.

Abstract: A SIMM (single in-line memory module) board is provided with a plurality of integrated semiconductor memory or other integrated semiconductor circuit devices which include, as a part of each integrated circuit device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the device to the board. By connecting the on-chip capacitors of the integrated circuit devices in parallel, sufficient capacitance is provided to stabilize current to all of the integrated circuit devices.

Abstract: A SIMM (single in-line memory module) board is provided with a plurality of integrated semiconductor memory or other integrated semiconductor circuit devices which include, as a part of each integrated circuit device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the device to the board. By connecting the on chip capacitors of the integrated circuit devices in parallel, sufficient capacitance is provided to stabilize current to all of the circuit devices.

Abstract: An extensive network of N-channel transistor formed capacitor, with one node tie directly to V.sub.CC power bus and the other node directly V.sub.SS power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 .mu.F.

Abstract: A Mask Write mode for a semiconductor memory responds to an enable command. This permits a by-four chip to provide parity information for four sectors of memory. The invention allows the latching of mask data on a rising edge of CAS so that new mask data can be entered in Page Mode.