Abstract: A SIMM (single in-line memory module) board is provided with a plurality of integrated semiconductor memory or other integrated semiconductor circuit devices which include, as a part of each integrated circuit device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the device to the board. By connecting the on-chip capacitors of the integrated circuit devices in parallel, sufficient capacitance is provided to stabilize current to all of the integrated circuit devices.

Abstract: Presented is an integrated circuit chip including a random access memory (RAM) array, serial access memory (SAM), an arithmetic logic unit, a bidirectional shift register, and masking circuitry. The arithmetic logic unit, SAM, shift register, and masking circuitry are all as wide as one side of the RAM array, and are all communicable with each other via data transfer means. This allows wide word processing, user configurable for parallel processing. Bits masked by the masking circuitry are selectable by data in the bidirectional shift register, providing shiftable masking means. Random access and serial access are done through separate ports. The bidirectional shift register is optionally serially accessible. Methods of use are also presented.

Abstract: Presented is an integrated circuit chip including a random access memory (RAM) array, serial access memory (SAM), an arithmetic logic unit, a bidirectional shift register, and masking circuitry. The arithmetic logic unit, SAM, shift register, and masking circuitry are all as wide as one side of the RAM array, and are all communicable with each other via data transfer means. This allows wide word processing, user configurable for parallel processing. Bits masked by the masking circuitry are selectable by data in the bidirectional shift register, providing shiftable masking means. Random access and serial access are done through separate ports. The bidirectional shift register is optionally serially accessible. Methods of use are also presented.

Abstract: To enhance the speed at which dynamic random access memories are refreshed, each sensing amplifier is provided with a clamping transistor. The clamping transistor is connected to a preselected voltage source. The clamping transistor prevents the voltage on the low-going bit line from falling to circuit ground by clamping the voltage on the low-going bit line to the preselected voltage.

Abstract: A SIMM (single in-line memory module) board is provided with a plurality of semiconductor memory devices which include, as a part of each memory device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the memory device to the board. By connecting the on-chip capacitors of the memory devices in parallel, sufficient capacitance is provided to stabilize current to all of the memory devices.

Abstract: An extensive network of N-channel transistor formed capacitor, with one node tie directly to V.sub.cc power bus and the other node directly V.sub.ss power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 .mu.F.

Abstract: A more secure method for selecting and addressing individual integrated circuit chips and memory locations, registers or input/output ports within the chips includes supplying the chips with address information including address checking information, checking the address information actually received in the chip by using an address checking circuit in the integrated circuit, and inhibiting use of the address information in the chip when the address checking circuit indicates an erroneous address. By inhibiting the use of erroneous address information, state information stored in the integrated circuit is not lost. The integrated circuit sends a fault signal requesting retransmission of the address information for recovery from the address fault. Preferably the address checking information is an error detecting and correcting code for correcting single-bit errors and detecting double-bit errors. Then the integrated circuit functions properly with one defective address input.

Abstract: A DRAM controller uses logic to selectively enable or disable a page mode of operation as a result of specific instructions from executing software, or upon some prediction of page mode efficiency based on past performance. An address multiplexer generates separate row and column addresses from the CPU address control lines, and to generate the necessary signals to control the timing of the RAS and CAS control signals that operate the DRAM. Page mode is automatically turned on or off based on a prediction of whether or not the next access will be at the same DRAM row address as the last one.

Abstract: A tailored edge rate triggers a pulldown device which turns on a sense amplifier in a memory array to sense and amplify a voltage difference between two digit lines, facilitating a memory cell read operation. The tailored edge rate activates the pulldown device slowly at first, then quickly saturates it, to allow transistors in the sense amplifier to activate and quickly sense the digit lines without bouncing same.

Abstract: An improved CMOS fabrication process which uses separate masking steps to pattern N-channel and P-channel transistor gates from a single layer of conductively-doped polycrystalline silicon (poly). The object of the improved process is to reduce the cost and improve the reliability and manufacturability of CMOS devices by dramatically reducing the number of photomasking steps required to fabricate transistors. By processing N-channel and P-channel devices separately, the number of photomasking steps required to fabricate complete CMOS circuitry in a single-polysilicon-layer or single-metal layer process can be reduced from eleven to eight. Starting with a substrate of P-type material, N-channel devices are formed first, with unetched poly left in the future P-channel regions until N-channel processing is complete. The improved CMOS process provides the following advantages over conventional process technology.

Abstract: An improved die-mounting paddle for mechanical stress reduction in plastic integrated circuit packages. The paddle, which is incorporated in a leadframe, comprises multiple, coplanar floating sub-paddles, each of which is attached to a support beam by a flexible coil, thus allowing a large die to remain firmly attached to each of the pads, in spite of differences in the coefficients of expansion between the leadframe paddle metal and the die that might well result in bonding wire breakage or die breakage if a conventional single large paddle were utilized.

Abstract: I/O lines on a CMOS circuit are precharged to preferred voltage levels in order to avoid latch up. The precharging is achieved by using N channel transistors to provide a precharge which is at a threshold voltage (V.sub.T) below bias voltage V.sub.CC, or (V.sub.CC -V.sub.T). This results in a lower forward bias when V.sub.CC bumps down after the I/O lines are floated. By lowering the precharge voltage by a level corresponding to a threshold voltage (V.sub.T), the allowed range of power supply voltage bumping is increased by this amount. This eliminmates the destructive effect of a negative bump of V.sub.BE, which would have presented a diode forward bias condition. Instead, the power supply may bump to (V.sub.BE +V.sub.T).

Abstract: A voltage sensing circuit is used to rapidly pull up a high potential node of a reference array to a value of a high potential source reduced by a threshold voltage (V.sub.CC -V.sub.T). During an enable cycle, the high potential node is precharged to a potential of V.sub.CC -V.sub.T, which turns on a transistor gated to the V.sub.CC potential. This pulls the high potential node as rapidly as possible to a high level in order to speed up the sensing process. A potential maintenance circuit provides sufficient current from the high potential source to maintain a desired potential at the high potential node.

Abstract: A memory array (e.g., DRAM) is provided with a potential maintenance circuit which provides sufficient current to maintain a high potential node of the memory array at a predetermined potential. The potential maintenance circuit is gated ON after receipt of a clock signal and gated OFF at the predetermined potential. This permits the high voltage node to be maintained, while reducing current requirements. The invention is particularly useful when used in conjunction with a circuit which rapidly pulls up the high node to a value of V.sub.CC -V.sub.T (where VT is a threshold voltage of a transistor).

Abstract: A pumpdown circuit uses voltage sensing to bring a low node to a potential of V.sub.SS +V.sub.T by first grounding the node and then floating the node to the V.sub.SS +V.sub.T potential. When a sensing node is at the V.sub.SS +V.sub.T potential, the sensing node is maintained at a level above ground by leakage current through a pump-up circuit. Biasing the digit and digit* lines to a potential V.sub.T above ground reduces current (amperage) requirement, because the digit and digit* lines do not have to be discharged completely to ground. The momentary discharge of the sense amp node to ground allows the sense amp to behave like a conventional sense amp during initial sensing, thereby allowing a minimum digit/digit* sensing potential to approximate ground plus V.sub.T.

Abstract: A new and improved solid-state image sensor uses a dynamic random access memory as the light sensitive element. The dynamic random access memory is mounted in a semiconductor package having a transparent lid, and one or more lenses focuses the light image onto the dynamic random access memory. A recording device or a display unit is provided. The new and improved solid-state sensor is particularly useful in low-cost applications, such as robots and toys.

Abstract: A circuit is provided for biasing the bit lines of a static semiconductor memory when each of the cells (150) within the memory is being powered by a backup power source due to failure of the primary power source. The bit lines (52) connected to the cells within the array (50) are connected to transistors (54) which bias the bit lines (52) to a high voltage upon detection of failure of the primary power for the computer. The bit lines (52) are maintained at a high voltage level to prevent discharge of a data storage node (156) through an access transistor (164) of a memory cell (150). Biasing of the bit lines (52) further prevents the integrated circuit substrate (150) from being driven excessively positive by capacitive coupling between the substrate (150) and the bit lines (52) when the primary power is restored to the circuit.

Abstract: An integrated circuit is disclosed which includes a charge pump adapted for biasing the substrate of a monolithic integrated circuit containing bipolar transistors. An oscillator operating under the control of a control input provides pulsed output signals for driving a diode-capacitor voltage multiplier network which generates a substrate bias voltage. A feedback network including a zener diode senses the substrate voltage, and switching action of the zener diode operates to selectively enable and disable the oscillator for regulating the substrate bias voltage.

Abstract: A unique topography of I.sup.2 L bipolar semiconductor elements provides Read-Write Random Access Memory (RAM) with very high packing density, low cost, and good power and speed characteristics and with a very simple metallization pattern.