Abstract: An integrated line selection apparatus within active matrix arrays is described. The circuit includes multiple gate line drive transistor devices, each gate line drive transistor device having a drain coupled to a gate line of multiple gate lines in a gate line driver circuit coupled to an active matrix array and a source to receive an input signal. The circuit further includes at least one address line transistor device corresponding to each gate line transistor device, each address line transistor device having a drain coupled to a gate of the corresponding gate line drive transistor device and a gate coupled to a corresponding address line, such that by asserting a predetermined combination of voltages on the plurality of address lines, a single gate line of said plurality of gate lines is selected to receive the input signal to be transmitted to a corresponding pixel within the corresponding active matrix array.

Abstract: This invention provides a method of forming at least one pressure switch thin film device. The method includes providing a substrate and depositing a plurality of thin film device layers as a stack upon the substrate. An imprinted 3D template structure is provided upon the plurality of thin film device layers. The plurality of thin film device layers and the 3D template structure are then etched and at least one thin film device layer is undercut to provide a plurality of aligned electrical contact pairs and adjacent spacer posts. A flexible membrane providing a plurality of separate electrical contacts is deposited upon the spacer posts, the separate electrical contacts overlapping the contact pairs. The spacer posts provide a gap between the electrical contacts and the contact pairs.

Abstract: A fabrication process for a device such as a backplane for a flat panel display includes depositing thin film layers on a substrate, forming a 3D template overlying the thin film layers, and etching the 3D template and the thin film layers to form gate lines and transistors from the thin film layers. An insulating or passivation layer can then be deposited on the gate lines and the transistors, so that column or data lines can be formed on the insulating layer.

Abstract: The subject invention concerns an electroporation buffer that allows for enhanced transfection efficiency and cell viability of cells during application of an electric current. Buffers of the invention provide for maximum transfer of target particles into cells while maintaining the health and growth potential of the cell population. Compositions of the invention comprise electroporation buffers of approximately physiological ionic strength and pH, and having serum or purified proteins, such as serum albumin, added thereto. The subject invention is suitable for use with any cell type. The subject invention also concerns methods of electroporation using an electroporation buffer of the invention.

Abstract: This invention provides a thin film device with minimized spatial variation of local mean height. More specifically, the thin film device has a substrate and at least one first structure having a first spatially varying weighted local mean height determined by a layer weighting function. The first structure has a first maximum height, a first minimum height and a first variation for a given averaging area. A compensation structure is also provided upon the substrate, the compensation structure having a second spatially varying weighted local mean height determined by the layer weighting function. The compensation structure also has a second maximum height, a second minimum height and a second variation for the given averaging area. The first structure and compensation structure combine to provide a combined structure upon the substrate with minimized spatial variation of a combined weighted local mean.

Abstract: Disclosed is an anti-counterfeiting system. In a particular embodiment, the anti-counterfeiting system has a first structure having a plurality of three-dimensional nanostructures, each having a height dimension less than a wavelength of visible light. In addition, there is a second structure having a second plurality of three-dimensional nanostructures, each having a height dimension less than a wavelength of visible light. The first and second structures are configured to couple together. An alignment mechanism is operable to align the first structure to the second structure and establish proximate contact between the first and second pluralities of nanostructures. With respect to the first and second structures, each encodes part of an authentication key. The authentication key includes pre-determined elements and interaction modalities. The resolution of the structures makes them copy-resistant. An associated method of use is also provided.

Abstract: This invention provides a thin film device with layer isolation structures. Specifically, a plurality of patterned thin film device layers provide a first rail and a second rail. There is at least one overpass between the first rail and the second rail. The overpass is defined by an array of spaced holes disposed transversely through the continuous material of the first rail on either side of the overpass. The holes are in communication with isolation voids adjacent to the second rail adjacent to the overpass.

Abstract: This invention provides a method of forming at least one pressure switch thin film device. The method includes providing a substrate and depositing a plurality of thin film device layers as a stack upon the substrate. An imprinted 3D template structure is provided upon the plurality of thin film device layers. The plurality of thin film device layers and the 3D template structure are then etched and at least one thin film device layer is undercut to provide a plurality of aligned electrical contact pairs and adjacent spacer posts. A flexible membrane providing a plurality of separate electrical contacts is deposited upon the spacer posts, the separate electrical contacts overlapping the contact pairs. The spacer posts provide a gap between the electrical contacts and the contact pairs.

Abstract: Provided is an article of manufacturer with anti-counterfeit properties a consumable, having taggant nanoparticles dispersed within it. Each taggant nanoparticle has at least one known physical characteristic such as, the taggant nanoparticles being a predetermined combination of nanoparticles providing at least two different taggant physical characteristics as a taggant code encoding product identification for the consumable so as to permit identification of the consumable. The physical characteristics in an embodiment include a combination of fluorescence, particle size, shape, and/or magnetic properties.

Abstract: An apparatus and method for measuring and monitoring layer properties in web-based processes are described. The apparatus includes multiple electrode devices adjacently positioned on a surface of a web material, which advances with a predetermined speed. The electrode devices perform measurements of electrical parameters of a layer of the web material and provide an electrical signal to a layer deposition system for further adjustment of layer properties of the layer.

Abstract: An integrated line selection apparatus within active matrix arrays is described. The circuit includes multiple gate line drive transistor devices, each gate line drive transistor device having a drain coupled to a gate line of multiple gate lines in a gate line driver circuit coupled to an active matrix array and a source to receive an input signal. The circuit further includes at least one address line transistor device corresponding to each gate line transistor device, each address line transistor device having a drain coupled to a gate of the corresponding gate line drive transistor device and a gate coupled to a corresponding address line, such that by asserting a predetermined combination of voltages on the plurality of address lines, a single gate line of said plurality of gate lines is selected to receive the input signal to be transmitted to a corresponding pixel within the corresponding active matrix array.

Abstract: Embodiments of the present invention include hierarchically-dimensioned, microfiber-based dry adhesive materials featuring dense arrays of microfibers with free tips terminating in numerous microfibrils. In certain embodiments, more than two levels of microfiber-dimension hierarchy may be employed, each dimension involving smaller microfibrils emanating from the tips of the microfibers or microfibrils of the next highest dimensional level. Various additional embodiments of the present invention are directed to methods for preparing hierarchically-dimensioned, microfiber-based dry adhesive materials. These methods include single-pass or multi-pass imprint-lithography, pattern masking and etching, and imprinting fiber-embedded substrates followed by etching.

Abstract: A method and system for facilitating etching. Specifically, the method includes incorporating a fluorescent marker in a layer of a grouping of patterned layers. Etching of the group of patterned layers is controlled based upon the fluorescent marker.

Abstract: A large area display workstation provides a liquid crystal display, configured to produce an image. The electrical components of the liquid crystal display are disposed on a substrate through a large area fabrication technique. The workstation has a first, high-resolution video display, and the large area display is a second, lower-resolution file identification display. The computer displays a user-selected file in a high-resolution format on the high-resolution video display for manipulation, and displays a plurality of file indicators in a low-resolution format on the large area display.

Abstract: An apparatus and method for storage and retrieval of memory content including a storage structure containing a plurality of memory elements addressable as a two-dimensional array of memory content values, a reading circuit capable of retrieving the memory content values from a region of the two-dimensional array varying in size according to the desired memory readout resolution, an aggregating circuit capable of totaling the memory content values of the memory elements addressed by the reading circuit to produce an aggregate memory content value and a normalizing circuit capable of scaling the aggregate memory content value according to the number of memory elements in the contiguous region to produce an average memory content value of the desired memory readout resolution.

Abstract: Provided is an article of manufacturer with anti-counterfeit properties a consumable, having taggant nanoparticles dispersed within it. Each taggant nanoparticle has at least one known physical characteristic such as, the taggant nanoparticles being a predetermined combination of nanoparticles providing at least two different taggant physical characteristics as a taggant code encoding product identification for the consumable so as to permit identification of the consumable. The physical characteristics in an embodiment include a combination of fluorescence, particle size, shape, and/or magnetic properties.

Abstract: Disclosed is an anti-counterfeiting system. In a particular embodiment, the anti-counterfeiting system has a first structure having a plurality of three-dimensional nanostructures, each having a height dimension less than a wavelength of visible light. In addition, there is a second structure having a second plurality of three-dimensional nanostructures, each having a height dimension less than a wavelength of visible light. The first and second structures are configured to couple together. An alignment mechanism is operable to align the first structure to the second structure and establish proximate contact between the first and second pluralities of nanostructures. With respect to the first and second structures, each encodes part of an authentication key. The authentication key includes pre-determined elements and interaction modalities. The resolution of the structures makes them copy-resistant. An associated method of use is also provided.

Abstract: A system comprises a processing chamber for maintaining a hydrogen plasma at low pressure. The processing chamber has a long, wide, thin geometry to favor deposition of thin-film silicon on sheet substrates over the chamber walls. The sheet substrates are moved through between ends. A pair of opposing radio frequency electrodes above and below the workpieces are electrically driven hard to generate a flat, pancaked plasma cloud in the middle spaces of the processing chamber. A collinear series of gas injector jets pointed slightly up on a silane-jet manifold introduce 100% silane gas at high velocity from the side in order to roll the plasma cloud in a coaxial vortex. A second such silane-jet manifold is placed on the opposite side and pointed slightly down to further help roll the plasma and maintain a narrow band of silane concentration.

Abstract: The present invention includes a method and system for correcting web deformation during a roll-to-roll process. The present invention includes controllable mechanical components that are capable of dynamically adjusting the planarity of the web during the roll-to-roll process. By adjusting the web during the roll-to-roll process, the accuracy of the layer-to layer alignment of successive patterning steps is greatly increased thereby enabling the production of electronic structures with lower overlap capacitance and higher resolution. A first aspect of the present invention is a method for correcting web deformation during a roll-to-roll process. The method includes initiating a roll-to-roll process involving a flexible web substrate, detecting deformation in the flexible web substrate during the roll-to-roll process and dynamically aligning the flexible web substrate based on the detected deformation.

Abstract: Provided is a low cost system and method for forming electronic devices, especially large surface area devices. The process of imprint lithography is combined with alternate manufacturing techniques to fabricate the devices. Initially, a template imprints a three-dimensional pattern into a resist layer deposited on a flexible substrate. The resist layer is cured using ultraviolet light or other curing techniques. After curing, the 3-D pattern is modified using one of several techniques to include inkjetting, electrodeposition or laser patterning. In one embodiment, a semi-fluid material may be jetted into channels formed in the pattern, thereby forming conductive or insulating lead lines. Alternatively, a two-dimensional pattern may be jetted onto the resist layer. Final processing may include multiple etch-mask-etch steps. The integration of techniques into a single system provides a low cost, efficient method for manufacturing high quality, large surface area electronic devices.