Abstract: The present invention includes a method and system for correcting web deformation during a roll-to-roll process. The present invention includes controllable mechanical components that are capable of dynamically adjusting the planarity of the web during the roll-to-roll process. By adjusting the web during the roll-to-roll process, the accuracy of the layer-to layer alignment of successive patterning steps is greatly increased thereby enabling the production of electronic structures with lower overlap capacitance and higher resolution. A first aspect of the present invention is a method for correcting web deformation during a roll-to-roll process. The method includes initiating a roll-to-roll process involving a flexible web substrate, detecting deformation in the flexible web substrate during the roll-to-roll process and dynamically aligning the flexible web substrate based on the detected deformation.

Abstract: Provided is a low cost system and method for forming electronic devices, especially large surface area devices. The process of imprint lithography is combined with alternate manufacturing techniques to fabricate the devices. Initially, a template imprints a three-dimensional pattern into a resist layer deposited on a flexible substrate. The resist layer is cured using ultraviolet light or other curing techniques. After curing, the 3-D pattern is modified using one of several techniques to include inkjetting, electrodeposition or laser patterning. In one embodiment, a semi-fluid material may be jetted into channels formed in the pattern, thereby forming conductive or insulating lead lines. Alternatively, a two-dimensional pattern may be jetted onto the resist layer. Final processing may include multiple etch-mask-etch steps. The integration of techniques into a single system provides a low cost, efficient method for manufacturing high quality, large surface area electronic devices.

Abstract: A specialized processor includes an objective function evaluator responsive to a state vector; and a solver, responsive to an output of the evaluator, for finding an optimal solution to the state vector. The processor can form a building block of a larger system.

Abstract: An silver island anti-fuse including a first electrical conductor, an electrically resistive material in contact with the first conductor and at least one silver island disposed opposite the first electrical conductor and upon the electrically resistive material. A second electrical conductor disposed over the silver island intimately couples the silver island to the electrically resistive material. When a critical potential is applied across the anti-fuse, a metallic filament precipitates from the silver island through the electrically resistive material layer, establishing a short and thus switching the silver island anti-fuse from a high resistance to a low resistance. A method of making the silver island anti-fuse and a memory device incorporating the silver island anti-fuse are further provided.

Abstract: An addressing circuit is operable to address one or more memory elements in a cross-point memory array. The addressing circuit includes first and second sets of address lines for addressing the cross-point memory array. The address circuit also includes pull-up and pull-down circuit elements. Both the pull-up and pull-down circuit elements and the address lines include cross-point resistive elements.

Abstract: A two-terminal electronic isolation device has an anode, a cathode, an integral tunnel junction, and a current-injection layer. The current-injection layer comprises a silicon-rich oxide.

Abstract: Embodiments of the present invention include hierarchically-dimensioned, microfiber-based dry adhesive materials featuring dense arrays of microfibers with free tips terminating in numerous microfibrils. In certain embodiments, more than two levels of microfiber-dimension hierarchy may be employed, each dimension involving smaller microfibrils emanating from the tips of the microfibers or microfibrils of the next highest dimensional level. Various additional embodiments of the present invention are directed to methods for preparing hierarchically-dimensioned, microfiber-based dry adhesive materials. These methods include single-pass or multi-pass imprint-lithography, pattern masking and etching, and imprinting fiber-embedded substrates followed by etching.

Abstract: Embodiments of the present invention include hierarchically-dimensioned, microfiber-based dry adhesive materials featuring dense arrays of microfibers with free tips terminating in numerous microfibrils. In certain embodiments, more than two levels of microfiber-dimension hierarchy may be employed, each dimension involving smaller microfibrils emanating from the tips of the microfibers or microfibrils of the next highest dimensional level. Various additional embodiments of the present invention are directed to methods for preparing hierarchically-dimensioned, microfiber-based dry adhesive materials. These methods include single-pass or multi-pass imprint-lithography, pattern masking and etching, and imprinting fiber-embedded substrates followed by etching.

Abstract: A proposed feature vector for a first deign is received and an existing feature vector for an existing design is retrieved for a given task. The proposed design is evaluated against the existing design using task-based scores associated with each design and based on their performances for the given task.

Abstract: Apparatus and method for making a multi-layered storage structure includes forming a device layer on a single-crystal wafer, cleaving the device layer from the wafer, repeating the forming and cleaving to provide a plurality of cleaved device layers, and bonding the cleaved device layers together to form the multi-layered storage structure.

Abstract: A resistive cross point memory cell array comprising a plurality of word lines, a plurality of bit lines, a plurality of cross points formed by the word lines and the bit lines, and a plurality of memory cells, each of the memory cells being located at a different one of the cross points, wherein a first bit line comprises a distributed series diode along an entire length of the bit line such that each of the associated memory cells located along the first bit line is coupled between the distributed series diode and an associated word line.

Abstract: A method for developing and using real time applications for a dynamic system having a sensing subsystem, actuation subsystem, a control subsystem, and an application subsystem utilizes stochastic compute time algorithms. After optimization functions, desired state and constraints are received and detector data has been provided from a sensor subsystem, a statistical optimization error description is generated. From this statistical optimization error description a strategy is developed, including the optimization errors, within the control subsystem. An execution module within the control subsystem then sends an execution strategy to various actuators within the actuation subsystem.

Abstract: An aspect of the present invention is a method for forming a plurality of thin-film devices. The method includes providing a flexible substrate and utilizing a self-aligned imprint lithography (SAIL) process to form the plurality of thin-film devices on the flexible substrate.

Abstract: A memory array has a multiplicity of row conductors and a multiplicity of column conductors, the row conductors and column conductors being arranged to cross at cross-points, and has a memory cell disposed at each cross-point, each memory cell having a storage element and a control element coupled in series between a row conductor and a column conductor, and each control element including a silicon-rich insulator. Methods for fabricating the memory array are disclosed.

Abstract: A method for displaying facial features includes generating an image with facial features on a nonplanar surface and positioning the image on the nonplanar surface to indicate a direction of gaze and enhance nonverbal communication associated with the facial features. The apparatus for displaying facial features includes a nonplanar surface, an image generation device that creates an image with facial features on the nonplanar surface and a positioning system that positions the image on the nonplanar surface to indicate a direction of gaze and enhance nonverbal communication associated with the facial features.

Abstract: Embodiments of organic-polymer-based memory elements that are stable to repeated READ access operations are disclosed. Organic-polymer-based memory elements can suffer cumulative degradation that occurs over repeated READ access operations due to the introduction of electrons into the organic-polymer layer. In general, entry of electrons into the organic-polymer layer generally lags initiation of a hole current within the organic-polymer layer following application of a voltage potential across the memory elements. Therefore, stable memory elements can be fabricated by introducing electron-blocking layers and/or limiting the duration of applied voltages during READ access operations.

Abstract: An addressing circuit is operable to address one or more memory elements in a cross-point memory array. The addressing circuit includes first and second sets of address lines for addressing the cross-point memory array. The address circuit also includes pull-up and pull-down circuit elements. Both the pull-up and pull-down circuit elements and the address lines include cross-point resistive elements.

Abstract: Apparatus and method for making a multi-layered storage structure includes forming a device layer on a single-crystal wafer, cleaving the device layer from the wafer, repeating the forming and cleaving to provide a plurality of cleaved device layers, and bonding the cleaved device layers together to form the multi-layered storage structure.

Abstract: A resistive cross point array memory device comprising a plurality of word lines extending in a row direction, a plurality of bit lines extending in a column direction such that a plurality of cross points is formed at intersections between the word and bit lines, and at least one memory element formed in at least one of the cross points. The memory element comprises a first tunnel junction having a bottom conductor, a top conductor, a barrier layer adjacent the bottom conductor, and wherein the bottom conductor comprises a non-uniform upper surface.

Abstract: The present invention includes a method and system for correcting web deformation during a roll-to-roll process. The present invention includes controllable mechanical components that are capable of dynamically adjusting the planarity of the web during the roll-to-roll process. By adjusting the web during the roll-to-roll process, the accuracy of the layer-to layer alignment of successive patterning steps is greatly increased thereby enabling the production of electronic structures with lower overlap capacitance and higher resolution. A first aspect of the present invention is a method for correcting web deformation during a roll-to-roll process. The method includes initiating a roll-to-roll process involving a flexible web substrate, detecting deformation in the flexible web substrate during the roll-to-roll process and dynamically aligning the flexible web substrate based on the detected deformation.