Patents by Inventor Warren M. Farnworth

Warren M. Farnworth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170320154
    Abstract: Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a bond pad of a microfeature workpiece, with the volume of material including a first metallic constituent and the bond pad including a second constituent. The method can further include elevating a temperature of the volume of material while the volume of material is applied to the bond pad to alloy the first metallic constituent and the second metallic constituent so that the first metallic constituent is alloyed generally throughout the volume of material. A thickness of the bond pad can be reduced from an initial thickness T1 to a reduced thickness T2.
    Type: Application
    Filed: July 24, 2017
    Publication date: November 9, 2017
    Inventors: Warren M. Farnworth, Rick C. Lake, William M. Hiatt
  • Patent number: 9737947
    Abstract: Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a bond pad of a microfeature workpiece, with the volume of material including a first metallic constituent and the bond pad including a second constituent. The method can further include elevating a temperature of the volume of material while the volume of material is applied to the bond pad to alloy the first metallic constituent and the second metallic constituent so that the first metallic constituent is alloyed generally throughout the volume of material. A thickness of the bond pad can be reduced from an initial thickness T1 to a reduced thickness T2.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: August 22, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Rickie C. Lake, William M. Hiatt
  • Publication number: 20170148691
    Abstract: Methods and systems for imaging and cutting semiconductor wafers and other microelectronic device substrates are disclosed herein. In one embodiment, a system for singulating microelectronic devices from a substrate includes an X-ray imaging system having an X-ray source spaced apart from an X-ray detector. The X-ray source can emit a beam of X-rays through the substrate and onto the X-ray detector, and X-ray detector can generate an X-ray image of at least a portion of the substrate. A method in accordance with another embodiment includes detecting spacing information for irregularly spaced dies of a semiconductor workpiece. The method can further include automatically controlling a process for singulating the dies of the semiconductor workpiece, based at least in part on the spacing information. For example, individual dies can be singulated from a workpiece via non-straight line cuts and/or multiple cutter passes.
    Type: Application
    Filed: February 7, 2017
    Publication date: May 25, 2017
    Inventors: Warren M. Farnworth, Tom A. Muntifering, Paul J. Clawson
  • Patent number: 9579825
    Abstract: Methods and systems for imaging and cutting semiconductor wafers and other microelectronic device substrates are disclosed herein. In one embodiment, a system for singulating microelectronic devices from a substrate includes an X-ray imaging system having an X-ray source spaced apart from an X-ray detector. The X-ray source can emit a beam of X-rays through the substrate and onto the X-ray detector, and X-ray detector can generate an X-ray image of at least a portion of the substrate. A method in accordance with another embodiment includes detecting spacing information for irregularly spaced dies of a semiconductor workpiece. The method can further include automatically controlling a process for singulating the dies of the semiconductor workpiece, based at least in part on the spacing information. For example, individual dies can be singulated from a workpiece via non-straight line cuts and/or multiple cutter passes.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: February 28, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Tom A. Muntifering, Paul J. Clawson
  • Patent number: 9337162
    Abstract: An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g., metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: May 10, 2016
    Assignee: Micron Technology, Inc.
    Inventors: William M. Hiatt, Warren M. Farnworth
  • Patent number: 9165888
    Abstract: Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Warren M. Farnworth, David R. Hembree
  • Patent number: 8951858
    Abstract: An imager device is disclosed including a first substrate having an array of photo-sensitive elements formed thereon, a first conductive layer formed above the first substrate, a first conductive member extending through the first substrate, the first conductive member being conductively coupled to the first conductive layer, a standoff structure formed above the first substrate, a second conductive layer formed above the standoff structure, the second conductive layer being conductively coupled to the first conductive layer, and an electrically powered device positioned above the standoff structure, the electrically powered device being electrically coupled to the second conductive layer.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Warren M. Farnworth
  • Patent number: 8929052
    Abstract: A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier. The conductor is removed from physically contacting the exposed conductive electrode. Dielectric material is applied over the conductive electrode. The substrate is treated while it is electrostatically bonded to the electrostatic carrier. In one embodiment, a conductor is forced through dielectric material that is received over a conductive electrode of an electrostatic carrier to physically contact the conductor with the conductive electrode to electrostatically bond a substrate to the electrostatic carrier. After removing the conductor from the dielectric material, the substrate is treated while it is electrostatically bonded to the electrostatic carrier. Electrostatic carriers for retaining substrates for processing, and such assemblies, are also disclosed.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: January 6, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Dewali Ray, Warren M. Farnworth, Kyle K. Kirby
  • Patent number: 8896105
    Abstract: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a method includes constructing a radiation sensitive component in and/or on a microelectronic device, placing a curable component in and/or on the microelectronic device, and forming a barrier in and/or on the microelectronic device to at least partially inhibit irradiation of the radiation sensitive component. The radiation sensitive component can be doped silicon, chalcogenide, polymeric random access memory, or any other component that is altered when irradiated with one or more specific frequencies of radiation. The curable component can be an adhesive, an underfill layer, an encapsulant, a stand-off, or any other feature constructed of a material that requires curing by irradiation.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: November 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Kristy A. Campbell
  • Publication number: 20140284375
    Abstract: Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a bond pad of a microfeature workpiece, with the volume of material including a first metallic constituent and the bond pad including a second constituent. The method can further include elevating a temperature of the volume of material while the volume of material is applied to the bond pad to alloy the first metallic constituent and the second metallic constituent so that the first metallic constituent is alloyed generally throughout the volume of material. A thickness of the bond pad can be reduced from an initial thickness T1 to a reduced thickness T2.
    Type: Application
    Filed: January 27, 2014
    Publication date: September 25, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Warren M. Farnworth, Rickie C. Lake, William M. Hiatt
  • Patent number: 8816463
    Abstract: The following disclosure describes several embodiments of (1) methods for wafer-level packaging of microelectronic imagers, (2) methods of forming electrically conductive interconnects in microelectronic imagers, (3) methods for forming optical devices for microelectronic imagers, and (4) microelectronic imagers that have been packaged using wafer-level packaging processes. Wafer-level packaging of microelectronic imagers is expected to significantly enhance the efficiency of manufacturing microelectronic imagers because a plurality of imagers can be packaged simultaneously using highly accurate and efficient processes developed for packaging semiconductor devices. Moreover, wafer-level packaging of microelectronic imagers is expected to enhance the quality and performance of such imagers because the semiconductor fabrication processes can reliably align an optical device with an image sensor and space the optical device apart from the image sensor by a desired distance with a higher degree of precision.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: August 26, 2014
    Assignee: Round Rock Research, LLC
    Inventors: Salman Akram, Peter A. Benson, Warren M. Farnworth, William M. Hiatt
  • Publication number: 20140206203
    Abstract: Semiconductor devices with porous insulative materials are disclosed. The porous insulative materials may include a consolidated material with voids dispersed therethrough. The voids may be defined by shells of microcapsules. The voids impart the dielectric materials with reduced dielectric constants and, thus, increased electrical insulation properties.
    Type: Application
    Filed: March 21, 2014
    Publication date: July 24, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Tongbi Jiang
  • Publication number: 20140206145
    Abstract: Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.
    Type: Application
    Filed: March 21, 2014
    Publication date: July 24, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Owen R. Fay, Warren M. Farnworth, David R. Hembree
  • Patent number: 8786097
    Abstract: Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from an active surface through a conductive element thereon and a portion of the substrate underlying the conductive element. The through via may then be completed by laser ablation or drilling from a back surface. In another embodiment, a partial via may be formed by laser ablation or drilling from the back surface of a substrate to a predetermined distance therein. The through via may be completed from the active surface by forming a partial via extending through the conductive element and the underlying substrate to intersect the laser-drilled partial via. In another embodiment, a partial via may first be formed by laser ablation or drilling from the back surface of the substrate followed by dry etching to complete the through via.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Charles M. Watkins, Kyle K. Kirby, Alan G. Wood, Salman Akram, Warren M. Farnworth
  • Patent number: 8704380
    Abstract: Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods are disclosed herein. A method for packaging microfeature devices in accordance with an embodiment of the invention can include releasably attaching a plurality of first known good microelectronic dies to a carrier substrate in a desired arrangement. In several embodiments, for example, the first dies can be releasably attached to an attachment feature on the carrier substrate. The method can also include attaching one or more second known good microelectronic dies to the individual first dies in a stacked configuration to form a plurality of stacked devices. The method further includes at least partially encapsulating the stacked devices and separating the stacked devices from each other.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood
  • Publication number: 20140083270
    Abstract: Methods and systems for imaging and cutting semiconductor wafers and other microelectronic device substrates are disclosed herein. In one embodiment, a system for singulating microelectronic devices from a substrate includes an X-ray imaging system having an X-ray source spaced apart from an X-ray detector. The X-ray source can emit a beam of X-rays through the substrate and onto the X-ray detector, and X-ray detector can generate an X-ray image of at least a portion of the substrate. A method in accordance with another embodiment includes detecting spacing information for irregularly spaced dies of a semiconductor workpiece. The method can further include automatically controlling a process for singulating the dies of the semiconductor workpiece, based at least in part on the spacing information. For example, individual dies can be singulated from a workpiece via non-straight line cuts and/or multiple cutter passes.
    Type: Application
    Filed: December 2, 2013
    Publication date: March 27, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Tom A. Muntifering, Paul J. Clawson
  • Patent number: 8680654
    Abstract: Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Warren M. Farnworth, David R. Hembree
  • Patent number: 8680680
    Abstract: Semiconductor devices with porous insulative materials are disclosed. The porous insulative materials may include a consolidated material with voids dispersed therethrough. The voids may be defined by shells of microcapsules. The voids impart the dielectric materials with reduced dielectric constants and, thus, increased electrical insulation properties.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Tongbi Jiang
  • Patent number: 8669179
    Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: March 11, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Charles M. Watkins, William M. Hiatt, David R. Hembree, James M. Wark, Warren M. Farnworth, Mark E. Tuttle, Sidney B. Rigg, Steven D. Oliver, Kyle K. Kirby, Alan G. Wood, Lu Velicky
  • Publication number: 20140042575
    Abstract: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a method includes constructing a radiation sensitive component in and/or on a microelectronic device, placing a curable component in and/or on the microelectronic device, and forming a barrier in and/or on the microelectronic device to at least partially inhibit irradiation of the radiation sensitive component. The radiation sensitive component can be doped silicon, chalcogenide, polymeric random access memory, or any other component that is altered when irradiated with one or more specific frequencies of radiation. The curable component can be an adhesive, an underfill layer, an encapsulant, a stand-off, or any other feature constructed of a material that requires curing by irradiation.
    Type: Application
    Filed: October 17, 2013
    Publication date: February 13, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Warren M. Farnworth, Kristy A. Campbell