Abstract: A semiconductor device according to an embodiment includes a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer and having a wider band gap than the first semiconductor layer, a source electrode and a drain electrode provided on the second semiconductor layer, wherein at least one of the source electrode and the drain electrode includes a plurality of protrusions on a side in contact with the second semiconductor layer, and a gate electrode provided between the source electrode and the drain electrode.

Abstract: A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.

Abstract: A semiconductor device of this embodiment includes: a first semiconductor layer including AlXGa1-XN; a second semiconductor layer provided above the first semiconductor layer, and including undoped or n-type AlYGa1-YN; a first and second electrodes provided above the second semiconductor layer; a third semiconductor layer provided above the second semiconductor layer between the first electrode and the second electrode, is at a distance from each of the first and second electrodes, and including p-type AlZGa1-ZN; a control electrode provided above the third semiconductor layer; a fourth semiconductor layer provided above the third semiconductor layer between the first electrode and the control electrode, is at a distance from the control electrode, and including n-type AlUGa1-UN; and a fifth semiconductor layer provided above a portion of the third semiconductor layer between the control electrode and the second electrode, is at a distance from the control electrode, and including n-type AlUGa1-UN.

Abstract: A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.

Abstract: According to one embodiment, the semiconductor element includes a semi-insulating substrate which has a first first-conductivity-type layer. The semiconductor element includes a first semiconductor layer. The first semiconductor layer contains non-doped AlXGa1-XN (0?X<1). The semiconductor element includes a second semiconductor layer. The second semiconductor layer contains non-doped or second-conductivity-type AlYGa1-YN (0<Y?1 and X<Y)). The semiconductor element includes a first major electrode and a second major electrode. The semiconductor element includes a control electrode provided on the second semiconductor layer between the major electrodes. And the first first-conductivity-type layer is provided under the control electrode.

Abstract: A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.

Abstract: A nitride semiconductor device includes a substrate, a first Inx1Ga1-x1-y1Aly1N layer, a second Inx2Ga1-x2-y2Aly2N layer, an interlayer insulating film, a source electrode, a drain electrode, a first gate electrode, a Schottky electrode, a second gate electrode, an interconnection layer. The second Inx2Ga1-x2-y2Aly2N layer is provided on a surface of the first Inx1Ga1-x1-y1Aly1N layer. The second Inx2Ga1-x2-y2Aly2N layer has a wider band gap than the first Inx1Ga1-x1-y1Aly1N layer. The first gate electrode is provided between the source electrode and the drain electrode on a surface of the second Inx2Ga1-x2-y2Aly2N layer. The Schottky electrode is provided on the second Inx2Ga1-x2-y2Aly2N layer between the first gate electrode and the drain electrode. The second gate electrode is provided on the second Inx2Ga1-x2-y2Aly2N layer between the Schottky electrode and the drain electrode. The interconnection layer electrically connects the source electrode, the Schottky electrode, and the second gate electrode.

Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type. A second semiconductor layer of a second conductivity type is on the first semiconductor layer. A third semiconductor layer is on the second semiconductor layer. A fourth semiconductor layer is selectively in the first semiconductor layer. A first trench and second trench penetrate from a surface of the third layer through the second layer to reach the first layer. An embedded electrode is in the first trench. A control electrode is above the embedded electrode via an insulating film. A lower end of the second trench is connected to the fourth semiconductor layer. A first main electrode is electrically connected to the first layer. A second main electrode is provided in the second trench. A Schottky junction is formed by the first layer and the second main electrode at a sidewall of the second trench.

Abstract: A semiconductor device includes a semiconductor substrate and a plurality of gate electrodes including a part extended in a first direction in a plane parallel with the semiconductor substrate. The semiconductor substrate has a second semiconductor layer including a plurality of first conductive type pillars and second conductive type second pillars that are disposed on the first semiconductor layer, extending in the first direction in the plane parallel with the semiconductor substrate and in a third direction intersecting with a second direction orthogonal to the first direction, and arranged adjacent to each other in an alternate manner.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a first semiconductor region, a second semiconductor region, a first electrode, a first electrode and a conducting section. The substrate includes a conductive region and has a first surface. The first semiconductor region is provided on the first surface side of the substrate and includes AlXGa1-XN (0?X?1). The second semiconductor region is provided on a side opposite to the substrate of the first semiconductor region and includes AlYGa1-YN (0?Y?1, X?Y). The first electrode is provided on a side opposite to the first semiconductor region of the second semiconductor region and ohmically connects to the second semiconductor region. The conducting section electrically connects between the first electrode and the conductive region.

Abstract: A semiconductor device includes: a first semiconductor layer made of an AlxGa1-xN (0?x<1); a second semiconductor layer provided on the first semiconductor layer and made of an undoped or first conductivity type AlyGa1-yN (0<y?1, x<y); an anode electrode and a cathode electrode which are connected to the second semiconductor layer; and a third semiconductor layer of second conductivity type provided between the anode electrode and the cathode electrode when viewed from a direction perpendicular to an upper surface of the second semiconductor layer. The third semiconductor layer is depleted when a predetermined magnitude or more of voltage is applied between the anode electrode and the cathode electrode.

Abstract: According to one embodiment, a nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a third electrode, a first insulating film and a second insulating film. The first semiconductor layer includes a nitride semiconductor. The second semiconductor layer is provided on the first layer, includes a nitride semiconductor, and includes a hole. The first electrode is provided in the hole. The second electrode is provided on the second layer. The third electrode is provided on the second layer so that the first electrode is disposed between the third and second electrodes. The first insulating film is provided between the first electrode and an inner wall of the hole and between the first and second electrodes, and is provided spaced from the third electrode. The second insulating film is provided in contact with the second layer between the first and third electrodes.

Abstract: According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region.

Abstract: According to one embodiment a nitride semiconductor device includes a first, a second and a third semiconductor layer, a first and a second main electrode and a control electrode. The first layer made of a nitride semiconductor of a first conductivity type is provided on a substrate. The second layer made of a nitride semiconductor of a second conductivity type is provided on the first layer. The third layer made of a nitride semiconductor is provided on the second layer. The first electrode is electrically connected with the second layer. The second electrode is provided at a distance from the first electrode and electrically connected with the second layer. The control electrode is provided within a first trench via an insulating film. The first trench is disposed between the first and the second main electrodes, penetrates the third and the second layers, and reaches the first layer.

Abstract: A power semiconductor device includes first to fifth electrodes, first to sixth semiconductor layers, and several first pillar layers. The first semiconductor layer is formed on the first electrode. The second semiconductor layer is formed on the first semiconductor layer. Several first pillar layers are arranged parallel with the second semiconductor layer. The third and fourth semiconductor layers are formed on the second semiconductor layer. The fourth electrode is formed on the first pillar layer adjacent to the third semiconductor layer. The fifth electrode is formed on the first pillar layer adjacent to the fourth semiconductor layer. The concentration of dopant of the first pillar layer positioning between the first pillar layer under the fourth electrode and the first pillar layer under the fifth electrode is lower than the concentration of dopant of the first pillar layer under the fourth electrode and the first pillar layer under the fifth electrode.

Abstract: According to one or more embodiments of the present invention, a method for driving a power semiconductor device that has a source electrode, a drain electrode, a semiconductor layer formed between the source electrode and the drain electrode, a plurality of gate electrodes formed within the semiconductor layer, and a plurality of conductive layers that are formed between the gate electrodes and the drain electrode and in electrical communication with the gate electrodes. The method comprises providing a first electric potential to the source electrode, providing a second electric potential to the drain electrode, providing a third electric potential to the gate electrodes, providing a first electric potential to at least one of the conductive layers, and providing a third electric potential to at least another one of the conductive layers.

Abstract: According to one embodiment, a semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer and formed of a non-doped or n-type nitride semiconductor having a band gap wider than that of the first nitride semiconductor layer, a heterojunction field effect transistor having a source electrode, a drain electrode, and a gate electrode, a Schottky barrier diode having an anode electrode and a cathode electrode, and first and second element isolation insulating layers. The first element isolation insulating layer has a first end contacting with the drain electrode and the anode electrode, and a second end located in the first nitride semiconductor layer. The second element isolation insulating layer has a third end contacting with the cathode electrode, and a fourth end located in the first nitride semiconductor layer.

Abstract: A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.

Abstract: A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof.

Abstract: A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.