Patents by Inventor Wataru Yokozeki

Wataru Yokozeki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10944980
    Abstract: Provided is an image data processing method. First, decoding processing designed (step S1) in such a manner that a moving picture X is singly processed and that a moving picture Y and Z having low vertical resolutions can be combined together to be subjected to decoding processing. Subsequently, each of the moving picture X, Y, and Z is encoded (step S2). Next, encoded data of the moving picture X is singly decoded, and the moving picture X is restored and displayed on a display unit of the image processing device at a predetermined timing. Meanwhile, respective pieces of encoded data of the moving picture Y and Z are combined together and are decoded depending on respective display timings, and the moving picture X and Y are restored and further separated from each other to be displayed on the display unit at the respective timings (step S3).
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: March 9, 2021
    Assignee: AXELL CORPORATION
    Inventors: Takashi Morishige, Kazuki Kyakuno, Wataru Yokozeki
  • Publication number: 20200351510
    Abstract: Provided is an image data processing method for preventing decrease of a decoding processing capability of an image processing device even if the image processing device is included in a game machine on which many moving pictures having low resolutions are displayed. First, decoding processing is designed (step S1). For example, it is designed in such a manner that a moving picture X is singly processed and that a moving picture Y and a moving picture Z having low vertical resolutions can be combined together to be subjected to decoding processing. Subsequently, each of the moving picture X, the moving picture Y, and the moving picture Z is encoded (step S2). Next, encoded data of the moving picture X is singly decoded, and the moving picture X is restored and displayed on a display unit of the image processing device at a predetermined timing.
    Type: Application
    Filed: July 21, 2020
    Publication date: November 5, 2020
    Applicant: AXELL CORPORATION
    Inventors: Takashi Morishige, Kazuki Kyakuno, Wataru Yokozeki
  • Publication number: 20190327480
    Abstract: Provided is an image data processing method. First, decoding processing designed (step S1) in such a manner that a moving picture X is singly processed and that a moving picture Y and Z having low vertical resolutions can be combined together to be subjected to decoding processing. Subsequently, each of the moving picture X, Y, and Z is encoded (step S2). Next, encoded data of the moving picture X is singly decoded, and the moving picture X is restored and displayed on a display unit of the image processing device at a predetermined timing. Meanwhile, respective pieces of encoded data of the moving picture Y and Z are combined together and are decoded depending on respective display timings, and the moving picture X and Y are restored and further separated from each other to be displayed on the display unit at the respective timings (step S3).
    Type: Application
    Filed: December 1, 2017
    Publication date: October 24, 2019
    Applicant: AXELL CORPORATION
    Inventors: Takashi Morishige, Kazuki Kyakuno, Wataru Yokozeki
  • Patent number: 7567101
    Abstract: A frequency comparator compares frequencies of a reference clock and an output clock to output a frequency comparison signal. A frequency variable circuit is composed of a delay circuit, which has a plurality of inverting circuits connected in series, and a first selection circuit. The first selection circuit selects one of odd output signals outputted from odd-numbered inverting circuits, according to the frequency comparison signal to feedback the selected odd output signal to an input of the delay circuit as a feedback signal. A phase comparator compares phases of the reference clock and the output clock to output a phase comparison signal. A second selection circuit selects one of the odd output signals according to the phase comparison signal to output it as the output clock.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: July 28, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Wataru Yokozeki
  • Patent number: 7417914
    Abstract: A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-channel transistors into the ON state to select one of local blocks arranged in a column direction. A NAND element inverts the logical product of a signal output from a local block selected by a local block selection signal and a signal output from a block not selected and outputs a result obtained to put an n-channel transistor into the ON or OFF state. The n-channel transistor grounds a common bit line when it goes into the ON state. Each of the p-channel transistors is selected by a column switch (not shown) and send read data to a data bus.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: August 26, 2008
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Shimizu, Wataru Yokozeki
  • Publication number: 20070247956
    Abstract: A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-channel transistors into the ON state to select one of local blocks arranged in a column direction. A NAND element inverts the logical product of a signal output from a local block selected by a local block selection signal and a signal output from a block not selected and outputs a result obtained to put an n-channel transistor into the ON or OFF state. The n-channel transistor grounds a common bit line when it goes into the ON state. Each of the p-channel transistors is selected by a column switch (not shown) and send read data to a data bus.
    Type: Application
    Filed: June 15, 2007
    Publication date: October 25, 2007
    Inventors: Hiroshi Shimizu, Wataru Yokozeki
  • Patent number: 7248534
    Abstract: A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-channel transistors into the ON state to select one of local blocks arranged in a column direction. A NAND element inverts the logical product of a signal output from a local block selected by a local block selection signal and a signal output from a block not selected and outputs a result obtained to put an n-channel transistor into the ON or OFF state. The n-channel transistor grounds a common bit line when it goes into the ON state. Each of the p-channel transistors is selected by a column switch (not shown) and send read data to a data bus.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: July 24, 2007
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Shimizu, Wataru Yokozeki
  • Patent number: 7080270
    Abstract: An integrated circuit has a sleep switch, provided between a first power line and a second power line, which is constituted by a transistor of a first threshold voltage, and which becomes non-conducting in a sleep mode, and further has a latch circuit, connected to the second power line, which is constituted by a transistor of a second threshold voltage which is lower than the first threshold voltage, and a ferroelectric capacitor for storing data held in the latch circuit in accordance with the polarization direction of a ferroelectric film thereof. The integrated circuit also comprises a control signal generating circuit which, when returning to an active mode from the sleep mode, generates a plate signal for driving a terminal of the ferroelectric capacitor to generate a voltage in the latch circuit in accordance with the polarization direction, and generates a sleep signal for causing the sleep switch to conduct to thereby activate the latch circuit following the driving of the ferroelectric capacitor.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: July 18, 2006
    Assignee: Fujitsu Limited
    Inventors: Wataru Yokozeki, Shoichi Masui
  • Publication number: 20060098517
    Abstract: A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-channel transistors into the ON state to select one of local blocks arranged in a column direction. A NAND element inverts the logical product of a signal output from a local block selected by a local block selection signal and a signal output from a block not selected and outputs a result obtained to put an n-channel transistor into the ON or OFF state. The n-channel transistor grounds a common bit line when it goes into the ON state. Each of the p-channel transistors is selected by a column switch (not shown) and send read data to a data bus.
    Type: Application
    Filed: December 21, 2005
    Publication date: May 11, 2006
    Inventors: Hiroshi Shimizu, Wataru Yokozeki
  • Patent number: 7016238
    Abstract: A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-channel transistors into the ON state to select one of local blocks arranged in a column direction. A NAND element inverts the logical product of a signal output from a local block selected by a local block selection signal and a signal output from a block not selected and outputs a result obtained to put an n-channel transistor into the ON or OFF state. The n-channel transistor grounds a common bit line when it goes into the ON state. Each of the p-channel transistors is selected by a column switch (not shown) and send read data to a data bus.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: March 21, 2006
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Shimizu, Wataru Yokozeki
  • Patent number: 7002834
    Abstract: At switching normal operation mode to low power mode, a first switch disconnects a virtual power supply line and a normal power supply line in response to activation of a switch control signal. The power supply voltage to a first circuit block connected to the virtual power supply line is suspended during the low power mode. A second switch of a floating prevention circuit connects a node between output of the first circuit block and input of a second circuit block to a first voltage line in response to inactivation of the switch control signal during the low power mode. This prevents the input of the second circuit block from floating even without the power supply voltage supplied to the first circuit block, and therefore prevents feedthrough current from flowing through the second circuit block, which enables reduction in power consumption during the low power mode.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: February 21, 2006
    Assignee: Fujitsu Limited
    Inventor: Wataru Yokozeki
  • Publication number: 20060001464
    Abstract: A frequency comparator compares frequencies of a reference clock and an output clock to output a frequency comparison signal. A frequency variable circuit is composed of a delay circuit, which has a plurality of inverting circuits connected in series, and a first selection circuit. The first selection circuit selects one of odd output signals outputted from odd-numbered inverting circuits, according to the frequency comparison signal to feedback the selected odd output signal to an input of the delay circuit as a feedback signal. A phase comparator compares phases of the reference clock and the output clock to output a phase comparison signal. A second selection circuit selects one of the odd output signals according to the phase comparison signal to output it as the output clock.
    Type: Application
    Filed: September 1, 2005
    Publication date: January 5, 2006
    Inventor: Wataru Yokozeki
  • Publication number: 20050242377
    Abstract: A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide into element active region of the device, that is, a defect involved in conventional LOGOS type process, are disclosed. A non-LOCOS insulating device isolation block is formed in a semiconductor substrate. The non-LOCOS insulating device isolation block uses a field shield element isolation structure or trench type element isolation structure.
    Type: Application
    Filed: June 30, 2005
    Publication date: November 3, 2005
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kohei Eguchi, Yuichi Egawa, Shoichi Iwasa, Hideki Fujikake, Wataru Yokozeki, Tatsuya Kawamata
  • Patent number: 6934178
    Abstract: A nonvolatile data storage circuit has a data holding circuit having a storage node, and a plurality of ferroelectric capacitors one electrodes of which are connected to the storage node. In this nonvolatile data storage circuit, in store operations to write data from the data holding circuit to the ferroelectric capacitors, the timing of at least the rising or the falling of plate signals supplied to the other electrodes of the plurality of ferroelectric capacitors, is made different. During store operation, the timing of the plate signals applied to the plurality of ferroelectric capacitors connected to the storage node is shifted, so that coupling noise between the ferroelectric capacitors is dispersed and can be reduced, and data inversion of the data holding circuit can be prevented.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: August 23, 2005
    Assignee: Fujitsu Limited
    Inventors: Wataru Yokozeki, Shoichi Masui
  • Patent number: 6930344
    Abstract: A nonvolatile semiconductor memory device includes a substrate, a plurality of transistors formed on the substrate to constitute a latch, a plate line, and a pair of capacitors each including a lower electrode, a ferroelectric film, and an upper electrode, the pair of capacitors being provided in a layer situated above the substrate and below a metal wiring layer in which the plate line is formed.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: August 16, 2005
    Assignee: Fujitsu Limited
    Inventors: Wataru Yokozeki, Akio Itoh
  • Patent number: 6924663
    Abstract: A programmable logic device with ferroelectric configuration memories storing multiple configuration data sets. The device has programmable logic blocks, interconnections, and I/O blocks to provide desired logic functions. Those building blocks can be dynamically reconfigured by changing the selection of configuration data stored in the device's integral configuration memories. The configuration memories are divided into groups, so that they can be loaded concurrently with multiple configuration data streams. To protect the content of configuration memories from unauthorized access, the device employs an authentication mechanism that uses security IDs stored in the configuration memories. The device has a memory controller to provide an appropriate power supply sequence for ferroelectric memory cells to ensure the reliable data retention when the device is powered up or shut down.
    Type: Grant
    Filed: December 24, 2002
    Date of Patent: August 2, 2005
    Assignee: Fujitsu Limited
    Inventors: Shoichi Masui, Michiya Oura, Tsuzumi Ninomiya, Wataru Yokozeki, Kenji Mukaida
  • Patent number: 6917076
    Abstract: A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide into element active region of the device, that is, a defect involved in conventional LOCOS type process, are disclosed. A non-LOCOS insulating device isolation block is formed in a semiconductor substrate. The non-LOCOS insulating device isolation block uses a field shield element isolation structure or trench type element isolation structure.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: July 12, 2005
    Assignee: United Microelectronics Corporation
    Inventors: Kohei Eguchi, Yuichi Egawa, Shoichi Iwasa, Hideki Fujikake, Wataru Yokozeki, Tatsuya Kawamata
  • Publication number: 20050146976
    Abstract: A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-channel transistors into the ON state to select one of local blocks arranged in a column direction. A NAND element inverts the logical product of a signal output from a local block selected by a local block selection signal and a signal output from a block not selected and outputs a result obtained to put an n-channel transistor into the ON or OFF state. The n-channel transistor grounds a common bit line when it goes into the ON state. Each of the p-channel transistors is selected by a column switch (not shown and send read data to a data bus.
    Type: Application
    Filed: February 14, 2005
    Publication date: July 7, 2005
    Inventors: Hiroshi Shimizu, Wataru Yokozeki
  • Patent number: 6914797
    Abstract: First buffers of a first driver circuit generate voltages to be supplied to word lines, respectively. Second buffers of a second driver circuit operate in synchronization with the first buffers to generate voltages to be supplied to first substrate lines, respectively. Each second buffer, upon access to memory cells, supplies a voltage for lowering the threshold values of transfer transistors and driver transistors to its corresponding first substrate line, and supplies thereto a voltage for raising the threshold values of the transfer transistors and the driver transistors during standby. This can improve the operation speed at the time of accessing the memory cells and reduce the leak current during standby. This results in shortening the access time during the operation of the semiconductor memory and reducing the standby current during standby.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: July 5, 2005
    Assignee: Fujitsu Limited
    Inventors: Tetsuo Ashizawa, Wataru Yokozeki
  • Patent number: 6876587
    Abstract: A semiconductor memory device comprises a memory cell array, a decoder unit selecting a word line of the memory cell array, a first dummy cell array connected to a first dummy bit line and disposed with the memory cell array at a first location away from the decoder unit along the word line, a second dummy cell array connected to second dummy bit lines and disposed with the memory cell array at a second location away from the decoder unit along the word line, the second location being farther from the decoder unit than the first location, and a timing control unit determining timing of activation and deactivation of an internal control signal.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: April 5, 2005
    Assignee: Fujitsu Limited
    Inventors: Tetsuo Ashizawa, Wataru Yokozeki